3D Resistive Memory Array with Shared Bitline
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current semiconductor devices face challenges such as short channel effects and increased power dissipation as they approach sub-100 nm sizes, limiting the scalability of transistor-based memories, and alternative non-volatile memory devices like Fe-RAM, MRAM, and PCRAM have compatibility and reliability issues with silicon-based fabrication.
Innovation Solution
A multilayer vertically stacked memory device structure with a common bit line connecting vertical conductor structures across layers, using amorphous silicon as a resistive switching material and silver as a metal electrode, simplifies fabrication and reduces feature size, allowing for integration into a CMOS process flow.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If transistor-based memories are scaled down to sub-100 nm sizes, then device density is improved, but short channel effects and power dissipation increase
Solution Approach 1:
The patent transitions from planar 2D transistor structures to three-dimensional vertically stacked memory cells, where multiple memory layers are stacked along the vertical dimension. This dimensional change allows continued density improvement without further lateral scaling, avoiding short channel effects while maintaining device performance through the vertical stacking architecture
2Adaptability or versatility
If alternative non-volatile memory devices (Fe-RAM, MRAM, PCRAM) are used, then memory functionality is improved, but fabrication compatibility and device reliability deteriorate
Solution Approach 1:
The patent combines the resistive switching functionality of alternative memory devices with standard silicon-based CMOS fabrication processes. By integrating these functions into a unified structure using conventional semiconductor manufacturing techniques, the invention achieves both improved memory functionality and maintained fabrication compatibility
Solution Approach 2:
The patent modifies material parameters and device structure to enable resistive switching behavior using amorphous silicon and metal electrodes that are compatible with existing CMOS processes. By changing the physical and electrical parameters of the memory element while maintaining process compatibility, the invention achieves both functional improvement and manufacturing ease
3Adaptability or versatility
If multiple metallization layers are used for bitlines, then device functionality is improved, but manufacturing complexity increases
Solution Approach 1:
The patent implements a shared bitline architecture where a single bitline serves multiple memory cells across different wordlines. This universal bitline design allows one conductor to perform multiple functions by connecting to numerous memory elements, reducing the total number of metallization layers and simplifying the interconnect structure while maintaining full device functionality
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the number of metallization steps, decreases device size, and enhances integration density while maintaining reliability, addressing the limitations of existing memory technologies.
Implementation Method 1
a resistive switching material conformably configured overlying a via structure
Implementation Method 2
A metal material is formed in a second portion of the via opening overlying the amorphous silicon material and substantially filling the via opening
Data Source
AI summary
A method of forming a non-volatile memory device. The method forms a vertical stack of first polysilicon material and a second polysilicon material layer isolated by a dielectric material. The polysilicon material layers and the dielectric material are subjected to a first pattern and etch process to form a first wordline associated with a first switching device and a second wordline associated with a second switching device from the first polysilicon material layer, and a third wordline associated with a third switching device and a fourth wordline associated with a fourth switching device from the second polysilicon material. A via opening is formed to separate the first wordline from the second wordline and to separate the third wordline from the fourth wordline. An amorphous silicon switching material is deposited conformably overlying the via opening. A metal material fills the via opening and connects to a common bitline.