3D RRAM Vertical Stacking for CMOS Integration
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Solution Overview
Problem
Current manufacturing methods for high-density 3D resistive random access memory (RRAM) require deep etching and filling processes, making it difficult to integrate with advanced logic processes like CMOS.
Innovation Solution
A RRAM structure and manufacturing method where memory cells are vertically arranged with isolated variable resistance structures and interconnects, eliminating the need for deep etching and filling processes by using a dielectric layer and conductive lines formed through chemical vapor deposition and damascene methods, allowing integration with advanced logic processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If deep etching and filling processes are used to manufacture high-density 3D RRAM, then memory density is improved, but manufacturing complexity and difficulty of integration with advanced logic processes increases
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking, where multiple memory cell layers are stacked along the vertical direction. This dimensional change enables high memory density without requiring deep etching and filling processes, as each layer can be formed using standard planar fabrication techniques followed by vertical stacking.
Solution Approach 2:
The memory structure is segmented into multiple independent memory cell layers stacked vertically, with each layer containing complete memory cells with variable resistance structures. This segmentation allows each layer to be manufactured using standard processes, avoiding the need for complex deep etching and filling while achieving high density through vertical stacking.
2Volume of moving object
If deep etching and filling processes are used for 3D RRAM manufacturing, then vertical memory cell arrangement is achieved, but compatibility with advanced logic processes deteriorates
Solution Approach 1:
The patent achieves vertical memory cell arrangement by stacking complete memory cell layers in the vertical dimension, rather than etching deep trenches to form vertical structures. This approach uses standard planar fabrication processes for each layer, ensuring compatibility with advanced logic process manufacturing, while still achieving the desired vertical 3D arrangement for high density.
3Area of stationary object
If vertically adjacent memory cells share conductive lines, then device area is reduced, but parasitic capacitance increases
Solution Approach 1:
The patent implements selective sharing of conductive lines based on local requirements. Word lines are shared horizontally across memory cells in the same layer, while bit lines are shared vertically across layers through via connections. This localized sharing strategy reduces device area while minimizing parasitic capacitance by optimizing the sharing topology for each conductive line type and location.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables direct integration with advanced logic processes, reduces parasitic capacitance, and simplifies the manufacturing process by avoiding deep etching and filling, while maintaining high-density memory cell arrangement.
Implementation Method 1
formed through chemical vapor deposition and damascene methods
Implementation Method 2
formed through chemical vapor deposition and damascene methods
Data Source
AI summary
A resistive random access memory including a substrate, a dielectric layer, and at least one memory cell string is provided. The dielectric layer is disposed on the substrate. The memory cell string includes memory cells and at least one first interconnect structure. The memory cells are vertically and adjacently disposed in the dielectric layer, and each memory cells includes a first conductive line, a second conductive line, and a variable resistance structure. The second conductive line is disposed at one side of the first conductive line, and the top surface of the second conductive line is higher than the top surface of the first conductive line. The variable resistance structure is disposed between the first conductive line and the second conductive line. The variable resistance structures in the vertically adjacent memory cells are isolated from each other. The first interconnect structure is connected to the vertically adjacent first conductive lines.