3D Security Processor Memory Wall Bottleneck
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Solution Overview
Problem
Conventional computer-security systems face performance issues due to limited core capabilities and the 'memory wall' in von Neumann architecture, which hinder efficient pattern processing for large virus databases, leading to poor anti-malware performance.
Innovation Solution
A 3-D security processor with a monolithic integrated circuit comprising storage-processing units, where a three-dimensional memory array is stacked above the pattern-processing circuit, eliminating the need for external storage and reducing latency through direct, short connections via contact vias, enabling increased storage capacity and processing power.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional von Neumann architecture is used with separated processor and storage, then device complexity is reduced and ease of manufacture is improved, but processing speed deteriorates due to memory wall and latency increases
Solution Approach 1:
The patent merges the processor and storage into a single integrated unit where memory cells are directly coupled to processing circuits. This eliminates the memory wall by allowing processing circuits to directly access and operate on stored data without external memory interfaces, thereby improving processing speed while accepting increased device complexity through integration.
Solution Approach 2:
The patent transitions from two-dimensional planar integration to three-dimensional vertical stacking, with memory cells stacked above processing circuits and connected via through-silicon vias. This dimensional change enables simultaneous access to multiple memory layers by different processing circuits, dramatically improving processing speed and bandwidth while managing device complexity through vertical architecture.
2Measurement precision
If virus database size is increased to improve detection capability, then measurement precision is improved, but processing time increases due to limited core capabilities
Solution Approach 1:
The patent segments the virus database into multiple memory cells distributed across a large array, with each processing circuit capable of independently accessing and comparing against portions of the database. This segmentation enables parallel processing of multiple virus patterns simultaneously, maintaining high detection accuracy with large databases while reducing processing time through concurrent operations.
Solution Approach 2:
The processing circuits are designed with universal pattern-matching capabilities that can compare input data against any stored virus pattern. Each processing circuit can handle multiple comparison operations simultaneously, enabling the system to efficiently search through expanded virus databases without proportionally increasing processing time, thus maintaining detection accuracy while scaling capacity.
3Productivity
If number of processing cores is increased to improve parallelism, then productivity is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent achieves high parallelism by stacking multiple layers of memory and processing circuits vertically, with each layer containing multiple processing circuits that can operate simultaneously. This three-dimensional architecture provides massive parallel processing capability without proportionally increasing the device footprint or manufacturing complexity, as multiple cores share common input/output interfaces and control logic.
Solution Approach 2:
The patent merges multiple processing circuits and memory cells into a tightly integrated array where shared resources such as word lines, bit lines, and control signals serve multiple processing units. This merging reduces the overall device complexity compared to having fully independent processing cores, while still achieving high productivity through parallel operation of multiple integrated processing elements.
Data Source
AI summary
The present invention discloses a processor for enhancing computer security, i.e. a three-dimensional (3-D) security processor. It is a monolithic integrated circuit comprising a plurality of storage-processing units (SPU). Each SPU comprises at least a three-dimensional memory (3D-M) array for permanently storing virus patterns and a pattern-processing circuit for performing pattern processing on a scanned computer data against said virus patterns. The 3D-M array is stacked above the pattern-processing circuit.