3D Semiconductor Device With Attic-Level Programming Circuitry
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The development of true three-dimensional integrated circuits (3D ICs) faces challenges in yield and reliability due to complex architectures and the need for new manufacturing techniques, particularly in deep submicron process generations, where existing testing methods are not adequately effective.
Innovation Solution
The solution involves a semiconductor device with multiple transistor layers and metal interconnects, where programming circuitry is placed in an 'Attic' level above the functional circuitry, using Through Silicon Vias for bonding, and employing antifuse-based programmable logic elements for flexible interconnects and redundancy, enabling efficient testing and repair mechanisms.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If Through Silicon Via technology is used to bond multiple transistor layers to form true 3D ICs, then device integration density and functionality are improved, but yield and reliability deteriorate due to manufacturing complexity and testing difficulties
Solution Approach 1:
The patent transitions from traditional 2D IC testing to 3D IC testing by adding the vertical dimension through Through Silicon Via connections. The testing architecture extends scan chains and test signals across multiple stacked transistor layers, enabling comprehensive testing of interlayer connections and logic circuits in the third dimension while maintaining manufacturing yield and reliability
Solution Approach 2:
The patent introduces intermediate testing structures including scan flip-flops, multiplexers, and test signal routing circuits that mediate between external test equipment and the internal 3D logic circuits. These intermediary elements enable systematic testing of TSV connections and interlayer signaling without requiring direct access to all internal nodes
2Adaptability or versatility
If complex architectures are implemented in deep submicron process generations, then device functionality and integration are improved, but manufacturing yield and reliability worsen
Solution Approach 1:
The patent segments the complex 3D IC architecture into modular transistor layers, each containing discrete logic circuits that can be independently tested and characterized. The scan testing architecture divides the test process into sequential stages, testing individual layers and their interconnections separately before integrating the full system, thereby managing manufacturing complexity and improving yield
3Measurement precision
If new testing methods are developed for 3D ICs, then testing effectiveness is improved, but device complexity and manufacturing difficulty worsen
Solution Approach 1:
The patent implements a universal testing architecture that uses standardized scan flip-flops, multiplexers, and test signal routing circuits applicable across all 3D IC layers and configurations. This multi-functional testing framework can test various logic circuit types (AND, OR, NOT gates, flip-flops) and interconnection structures using the same basic test methodology, improving testing effectiveness without proportionally increasing device complexity
Data Source
AI summary
A semiconductor device includes a first transistor layer and a second transistor layer overlaying the first transistor layer, wherein said first transistor layer comprises a plurality of flip-flops each having a selectively coupleable additional input generated by said second transistor layer.