3D Semiconductor Devices With Crystal Plane Orientations
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Solution Overview
Problem
The integration of two-dimensional semiconductor devices is limited by the cost of processing equipment needed for fine pattern formation, leading to a practical limitation in increasing their integration density, while three-dimensional semiconductor devices offer a potential solution but require enhanced structural stability to overcome manufacturing challenges.
Innovation Solution
A three-dimensional semiconductor device is designed with a stack structure that includes gate electrodes, channel regions penetrating the stack, and a peripheral circuit structure on interlayer dielectric layers, where the substrates have specific crystal plane orientations to enhance structural stability and integration density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If two-dimensional semiconductor devices use finer patterns to increase integration density, then integration density is improved, but processing equipment cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar semiconductor devices to three-dimensional vertically stacked devices. Multiple memory cells are stacked in the vertical direction (third dimension) on a single substrate, enabling integration density to increase without requiring finer lateral patterning. This dimensional transition resolves the contradiction by achieving higher integration density while avoiding the need for expensive fine-patterning equipment.
2Quantity of substance
If three-dimensional semiconductor devices are constructed with stacked structures, then integration density is improved, but structural stability deteriorates
Solution Approach 1:
The patent employs substrate bonding technology where two substrates are bonded together to form a mechanically stable stacked structure. The bonding interface between substrates provides structural support, maintaining stability while enabling the vertical stacking configuration that increases integration density. This parameter change in structural configuration resolves the contradiction between three-dimensional stacking and structural stability.
Data Source
AI summary
Disclosed is a three-dimensional semiconductor device comprising channel regions that penetrate the stack structure and extend in a direction perpendicular to a top surface of the first substrate, a first interlayer dielectric layer on the stack structure, and a peripheral circuit structure on the first interlayer dielectric layer. The peripheral circuit structure includes peripheral circuit elements on a first surface of a second substrate. The peripheral circuit elements are electrically connected to the channel regions and at least one of the gate electrodes. The first substrate has a first crystal plane parallel to the top surface thereof. The second substrate has a second crystal plane parallel to the first surface thereof. An arrangement direction of atoms of the first crystal plane intersects an arrangement direction of atoms of the second crystal plane.