Digital Storage TRIZ Cases

Voltage control of magnetic anisotropy switches fixed skyrmions without spin currents, reducing energy dissipation in nanomagnetic memory.

A zero transistor bitcell uses a spin hall metal to generate diffusive spin torque current for writing magnetic states.

A shared counter tracks access counts for multiple word lines, reducing chip area and cost compared to dedicated counters.

A memory device stores calibration data and inverted bits in shared sections to generate compensation signals.

A semiconductor memory device enables test mode entry during active operation via dedicated control blocks.

A pseudo SRAM hidden refresh method generates a non-overlapping refresh clock signal to trigger memory operations independently of the system clock.

A semiconductor memory device integrates a hidden write operation using the CBR refresh command to simultaneously write data across all bit lines.

A semiconductor memory input latency control circuit gates address signals through pipeline stages to generate column and bank addresses.

Stacking bit storage and comparison tiers reduces die area and power consumption while maintaining high search speeds.

A two capacitor self-referencing nonvolatile bitcell stores flip-flop states using ferroelectric polarization without continuous power.

Floating storage nodes in a 4T-SRAM cell enable asymmetrical voltage detection, reducing leakage current while maintaining data stability.

A bank active signal generation circuit produces synchronized signals using decoded logic and transmission gates.

A readout circuit sense amplifier uses an isolation unit to disconnect from bit lines during offset cancellation.

A PRAM write driver circuit integrates a test driver to supply additional current for accelerated stress evaluation of phase change memory cells.

A nine transistor bitcell uses a pFET header to decouple nFET-pFET contention and accelerate write operations.

Sensor cells within a DRAM array detect electromagnetic disturbances to trigger targeted refresh cycles.

Switching circuit couples SRAM bitcell banks to recycle leakage current during retention mode.

A non-volatile computing register stores calculation results directly into ferroelectric cells during atomic transactions.

A capacitance network discharges at a rate controlled by a reference current from SRAM cells to generate a delay signal.

Delayed sensing circuits identify the lowest operating voltage and highest clock frequency, balancing performance against power consumption.

Glass-forming agents in the oxide interlayer reduce interdiffusion and lattice mismatch, increasing tunneling magnetoresistance while lowering magnetic damping.

A memory device tracks row access frequency using dedicated count cells and resets these values during normal refresh operations to mitigate row hammer effects.

A software programmable memory interface circuit adjusts timing offsets via digitally controllable delay elements for stable data transfers.

Laser stimulation maps sense signal changes to locate filaments without invasive electrical stress.

Stepping word line voltage through intermediate and high conductance levels reduces access disturbance in bit cells, improving data stability.

Separate counters capture row addresses before activation, preventing incorrect refresh operations on shared address paths.

A memory system coordinates devices with different latencies on a shared bus to increase data transfer size.

Reference path uses poly-resistor temperature coefficient to compensate for global PVT variations, eliminating high temperature refresh requirements.

A dual power supply memory system uses a translation circuit to eliminate level-shifting components, reducing latency and leakage.

Asymmetric bit-line pitch arranges memory stacks to consistently form conductive filaments along one side, reducing electrical resistance variations.

A variable resistance memory device uses a two-MTJ-per-cell structure to store data in sub-cells.

A memory line stores a compression marker at the front to detect status without reading the full data.

A reference voltage training method stores data for code signal combinations and outputs it simultaneously.

Dynamic negative body bias prevents data flip errors during parallel row access, maintaining accuracy without increasing circuit area.

A nanowire memory device nucleates a magnetic vortex in a pad and shifts the domain into the wire using spin transfer torque.

Three-dimensional semiconductor devices with specific substrate crystal plane orientations enhance structural stability and integration density.

Averaging paired reference MTJ elements establishes a stable comparison threshold for MRAM sense amplifiers.

A semiconductor device expands the output period of a data strobe signal using an expansion control signal during read operations.

External voltage drives the write circuit to boost data writing speed in variable resistance memory arrays.

A non-volatile memory cell applies a weak set voltage to stabilize the resistance state of its variable element.

Gear-down offset circuitry extends 1-0-1 transitions on the command bus, resolving timing margin losses during 1N to 2N mode switches.

A row decoder uses power gating to activate only selected memory cell groups during address decoding operations.

A charge sharing compute-in-memory bit cell uses internal capacitors to perform local operations.

Integrating current mirror circuits into SRAM read ports merges storage and computation, eliminating separate multipliers to reduce power consumption.

Ingress data placement logic bypasses the I/O adapter processor, reducing latency by routing host memory descriptors directly into device memory.

A data strobe control device synchronizes address latching with burst length signals to manage write paths in semiconductor memory.

Positioning repeaters selectively in specific core regions reduces layout area and power consumption by limiting signal amplification operations.

Cycle tracking circuitry adjusts sense voltage based on memory cell access counts to maintain accurate data interpretation.

A single-port memory device executes multiple read and write operations within one clock cycle using internal clock generation and self-timing path circuitry.

Lookahead tables adjust read pointers by prescribed frequency offsets, resolving latency and data accuracy trade-offs in asynchronous FIFOs.