SRAM Delay Circuit Tracking Bitcell Characteristics
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Solution Overview
Problem
Current SRAM devices face performance issues due to variable delays between word line activation and data readiness on bit lines, primarily because existing delay generation methods rely on logic devices that are susceptible to process, voltage, and temperature variations, leading to suboptimal performance and stability problems.
Innovation Solution
An SRAM circuit that generates a delay signal independent of logic devices by using a capacitance network controlled by a reference current from a set of reference SRAM cells, which dictates the discharge rate and activates an output circuit when a threshold voltage is exceeded, thereby tracking bitcell characteristics without modifying the fabrication layout.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If logic devices are used to generate delay, then delay generation is achieved, but performance deteriorates due to PVT variations and susceptibility to writability and stability problems
Solution Approach 1:
The patent creates a copy of the SRAM cell's timing characteristics by using identical SRAM cells as reference cells to generate a reference current. This reference current then controls the discharge rate of a capacitance network, effectively copying the cell's operational timing behavior into the delay circuit, thereby eliminating PVT variation issues associated with logic devices.
Solution Approach 2:
The patent changes the fundamental parameter used for delay generation from logic device timing (which is PVT-sensitive) to a current-based reference derived from SRAM cells themselves. By using the reference current to control capacitance discharge rate, the system transforms the delay generation mechanism to be inherently tied to SRAM cell characteristics rather than external logic devices.
2Reliability
If logic devices are used to generate delay, then delay signal is produced, but performance becomes suboptimal due to susceptibility to PVT variations
Solution Approach 1:
The patent uses reference SRAM cells to copy the timing characteristics of the actual SRAM cells. The reference current generated from these identical cells inherently reflects the same PVT conditions, thereby canceling out the harmful effects of PVT variations that would otherwise affect delay signal stability.
Solution Approach 2:
The system implicitly uses feedback by deriving the reference current from reference cells that are part of the SRAM array itself. This creates a self-regulating mechanism where the delay circuit automatically adapts to PVT changes through the reference cells' inherent characteristics, maintaining stable delay signals without external compensation.
3Measurement precision
If reference SRAM cells are used to generate reference current, then delay tracking of bitcell characteristics is achieved, but additional reference cells are required in the fabrication layout
Solution Approach 1:
The reference SRAM cells serve multiple functions: they act as both functional memory cells and as reference elements for generating the reference current. This multi-functionality allows the same physical cells to provide both storage capability and timing reference, thereby achieving accurate delay tracking without requiring separate dedicated reference cell structures.
Solution Approach 2:
The patent merges the reference function with the functional SRAM cell structure. By using the same cell architecture for both storage and reference purposes, the system combines multiple functions into a unified structure, reducing the overall complexity of the fabrication layout while maintaining measurement precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach provides a logic-device-independent delay signal that is less sensitive to random device variations, enhancing SRAM cell writability and stability by accurately timing bit line operations based on SRAM device characteristics.
Implementation Method 1
a capacitance network having a discharge rate that is controlled by the reference current
Implementation Method 2
using the reference current to dictate a discharge rate of a capacitance network onto a discharge line
Data Source
AI summary
An SRAM delay circuit that tracks bitcell characteristics. A circuit is disclosed that includes an input node for receiving an input signal; a reference node for capturing a reference current from a plurality of reference cells; a capacitance network having a discharge that is controlled by the reference current; and an output circuit that outputs the input signal with a delay, wherein the delay is controlled by the discharge of the capacitance network.