Non-Volatile Computing Register with Ferroelectric Retention
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Solution Overview
Problem
Existing systems face challenges in maintaining data retention during power-down modes in portable devices, as leakage currents and the need for continuous power to retain state information hinder efficient power management, especially in energy-harvesting applications where power is intermittent.
Innovation Solution
The implementation of non-volatile computing registers coupled with ferroelectric capacitors allows for atomic, uninterrupted storage of critical data directly into non-volatile memory cells, utilizing a fail-safe power source to ensure data preservation across power failures, eliminating the need for continuous power and enhancing security by preventing data exposure during updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If multi-threshold CMOS technology is used to reduce leakage current, then power consumption during standby mode is reduced, but device complexity increases due to additional latches and power supply requirements
Solution Approach 1:
The patent extracts the data retention function from the main logic circuit by using a separate shadow latch that can be powered down independently. This allows the main logic to be completely powered off while the shadow latch maintains state with minimal power, reducing both leakage current and the complexity of keeping the entire system powered.
Solution Approach 2:
The patent segments the power supply into two independent domains: a main power supply for active logic operations and a separate retention power supply for the shadow latch. This segmentation allows different parts of the circuit to operate under different power conditions, enabling low-power standby mode while maintaining data retention capability.
2Reliability
If a separate always-on power supply is used for data retention latch, then data retention reliability is improved, but power consumption increases
Solution Approach 1:
Instead of continuous power consumption, the retention latch uses periodic or intermittent power from the always-on power supply domain. The latch is powered only when needed to maintain state during power-down events, rather than continuously consuming power, thus reducing overall energy usage while maintaining reliability.
3Reliability
If non-volatile memory is used for data storage, then data retention across power failures is improved, but device complexity increases due to additional memory cells and control logic
Solution Approach 1:
The patent merges the shadow latch functionality with non-volatile memory cells to create a unified retention mechanism. The shadow latch is implemented using non-volatile memory that maintains state without requiring continuous power or separate retention circuits, combining multiple functions into a single integrated structure that reduces overall device complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution ensures reliable data retention across power failures, reduces power consumption, and enhances security by ensuring atomic transactions for data updates, even in the absence of a constant power source, making it suitable for energy-harvesting devices and preventing malicious data manipulation.
Implementation Method 1
non-volatile computing registers coupled with ferroelectric capacitors
Data Source
AI summary
A digital system includes a non-volatile calculating register having a set of latches configured to perform a calculation. A set of non-volatile storage cells is coupled to the set of latches. Access detection logic is coupled to the calculating register and is operable to initiate a calculation of a next value by the calculating register each time the calculating register is accessed by an accessing module. The access detection logic is operable to cause the next value to be stored in the set of non-volatile storage cells at the completion of the calculation as an atomic transaction. After a power loss or other restore event, the contents of the calculating register may be restored from the non-volatile storage cells.