Asymmetric Bit-Line Architecture for RRAM Read Window
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Solution Overview
Problem
In resistive random access memory (RRAM) devices, variations in the number, size, and location of conductive filaments between bit-line stacks lead to variations in electrical resistance, degrading the read window and impacting memory array performance.
Innovation Solution
The implementation of bit-line stacks at an asymmetric pitch, where one side of a bit-line stack is laterally separated from the word-line by a smaller distance than the opposing side, consistently forming a conductive filament along one side, reducing variations in conductive filaments between different bit-lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If bit-line stacks are arranged at symmetric pitch, then manufacturing process is simpler, but variations in conductive filaments increase leading to degraded read window
Solution Approach 1:
The patent applies asymmetry by arranging bit-line stacks at asymmetric pitch distances from word-lines, where first bit-line stacks are positioned at a first pitch distance and second bit-line stacks at a second pitch distance that differs from the first. This asymmetric arrangement consistently forms conductive filaments along only one side of each bit-line stack, reducing variations in filament number, size, and location between different bit-lines, thereby improving read window and memory array performance.
2Manufacturing precision
If conductive filaments form on both sides of bit-line stacks, then more storage locations are available, but variations in filament number and size increase resistance variability
Solution Approach 1:
The patent applies local quality by creating different spatial conditions at different locations around bit-line stacks. Specifically, the asymmetric pitch arrangement ensures that conductive filaments consistently form only along one side of each bit-line stack (where the pitch distance allows), while the other side (with different pitch distance) does not support filament formation. This localized control over filament formation reduces variations in electrical resistance across the memory array.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the performance of RRAM devices by minimizing variations in electrical resistance, enhancing the read window and overall memory array performance.
Implementation Method 1
a selector disposed over the data storage structure; and a word-line disposed over the selector. The selector is configured to selectively allow current to pass between the plurality of bit-lines and the word-line
Data Source
AI summary
The present disclosure relates to an integrated chip structure. The integrated chip structure includes a plurality of memory stacks disposed over a substrate and respectively having a plurality of conductive segments stacked onto one another. One or more data storage structures are on the plurality of memory stacks, one or more selectors are over the one or more data storage structures, and an upper conductor over the one or more selectors. The plurality of memory stacks include a first memory stack, a second memory stack, and a third memory stack. The first memory stack and the third memory stack are closest memory stacks to opposing sides of the second memory stack. The first memory stack is closer to the second memory stack than the third memory stack.