Shared Address Path Memory Bank Refresh Control
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Solution Overview
Problem
In semiconductor memory devices, refreshing one memory bank while accessing another using a shared address path often results in incorrect row addresses being used for refresh or access operations, leading to errors in data retrieval or storage.
Innovation Solution
Implementing a system where bank control blocks capture and increment row addresses stored in registers, and using a flip-flop to store and output row addresses, ensuring that refresh operations are performed on the correct rows while allowing access to other memory banks without confusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a single shared address path is used for both refresh and access operations, then device complexity is reduced, but reliability deteriorates due to incorrect row addresses being used for refresh or access operations
Solution Approach 1:
The patent segments the address handling by introducing separate counters for refresh operations (counter 0 and counter 1) distinct from the access operation address path. This segmentation allows independent tracking of refresh row addresses while maintaining a shared physical address bus, resolving the conflict between complexity reduction and reliability.
Solution Approach 2:
The patent introduces intermediate components including separate refresh counters, a multiplexer, and control logic that acts as mediators between the shared address path and the memory banks. These intermediaries ensure correct row address selection during refresh operations without requiring dedicated address paths, thus maintaining reliability while sharing the address infrastructure.
2Productivity
If multiple refresh operations are performed on one memory bank, then productivity is improved by refreshing multiple rows, but reliability deteriorates when an activate operation overwrites the stored row address
Solution Approach 1:
The patent performs preliminary actions by capturing and storing the row address in separate counters (counter 0 and counter 1) before any activate operation can overwrite it. The counters are updated in advance and protected from overwriting, ensuring that refresh operations have the correct row addresses ready before they are needed, thus preventing address corruption while enabling multiple refresh operations.
Solution Approach 2:
The patent creates copies of the row address in multiple separate counters (counter 0 for even banks, counter 1 for odd banks) rather than relying on a single stored address. This copying mechanism ensures that even if one counter is overwritten or becomes invalid, the correct row address remains preserved in the other counter, maintaining reliability during multiple refresh operations.
Data Source
AI summary
A system includes first and second sets of memory banks that store data. The system also includes an address path coupled to the memory banks that provides a row address to the memory banks. The system further includes a command address input circuit coupled to the address path. The command address input circuit includes a counter that stores and increments the row address. The system also includes a flip-flop that stores the row address in response to receiving a command to refresh the first set of memory banks.