Readout Circuit Sense Amplifier TRCD Delay Reduction
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Solution Overview
Problem
Conventional semiconductor memory devices face limitations in access speed and utilization efficiency due to the RAS-to-CAS delay (TRCD), which affects the read speed of dynamic random access memory (DRAM).
Innovation Solution
A readout circuit with a sense amplifier and an isolation unit, connected through an offset canceling unit, where the sense amplifier is disconnected from bit and complementary bit lines during offset cancellation and charge sharing, allowing these processes to occur simultaneously, thereby reducing TRCD and enhancing access speed.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the sense amplifier is connected to the bit line and complementary bit line continuously, then the read operation can be performed, but the offset cancellation and charge sharing cannot be performed simultaneously, resulting in increased TRCD delay
Solution Approach 1:
The patent applies the dynamics principle by making the connection between the sense amplifier and bit lines dynamic rather than static. The isolation unit selectively disconnects the sense amplifier from the bit line and complementary bit line during offset cancellation and charge sharing operations, allowing these operations to proceed in parallel without interfering with each other. This dynamic disconnection enables simultaneous execution of offset cancellation and charge sharing, thereby reducing TRCD delay while maintaining read accuracy.
Solution Approach 2:
The patent applies segmentation by dividing the operational timeline into distinct phases: a first period for offset cancellation where the sense amplifier is disconnected from bit lines, and a second period for charge sharing where the sense amplifier is reconnected. This temporal segmentation allows offset cancellation and charge sharing to occur in separate time windows, enabling both operations to be performed efficiently without mutual interference and reducing overall TRCD delay.
2Measurement precision
If the offset cancellation is performed before charge sharing, then the read accuracy is ensured, but the access speed is reduced due to sequential operations
Solution Approach 1:
The patent uses dynamic disconnection of the sense amplifier from bit lines during offset cancellation to enable parallel execution of offset cancellation and charge sharing operations. By making the connection state changeable, the system can perform offset cancellation when disconnected and charge sharing when connected, achieving both high precision and fast access speed through temporal parallelism.
Solution Approach 2:
The patent applies preliminary action by performing offset cancellation before charge sharing in a controlled manner. The isolation unit disconnects the sense amplifier from bit lines prior to the charge sharing operation, allowing offset cancellation to be completed in advance. This preliminary offset cancellation ensures read precision while the subsequent charge sharing operation can proceed in parallel, maintaining high access speed.
3Loss of time
If the sense amplifier is disconnected from bit lines during offset cancellation, then the TRCD delay is reduced, but the read operation requires additional control complexity
Solution Approach 1:
The patent introduces an isolation unit as an intermediary component between the sense amplifier and bit lines. This isolation unit mediates the connection and disconnection operations, controlling when the sense amplifier is connected to or disconnected from the bit lines during different operational phases. By using this intermediary device, the system achieves reduced TRCD delay through selective disconnection while managing control complexity through a dedicated control mechanism.
Data Source
AI summary
The present disclosure provides a readout circuit, a memory, and a method of reading out data of a memory. The readout circuit includes: a sense amplifier and an isolation unit, the sense amplifier being connected to a bit line and a complementary bit line through the isolation unit, the bit line being connected to a memory cell and the complementary bit line being connected to a memory cell, and the isolation unit being configured to disconnect the sense amplifier from the bit line and the complementary bit line in response to an isolation signal; and an offset canceling unit, configured to perform an offset cancellation on the sense amplifier in response to an offset canceling signal, at least a part of a stage of a charge sharing being performed at the same time as at least a part of a stage of an operation of the offset canceling unit.