SRAM Body Bias Modulation for In-Memory Compute Data Flip Prevention
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Solution Overview
Problem
In-memory computation circuits using standard 6T SRAM cells face data flip errors during simultaneous row access in matrix vector multiplication operations, leading to accuracy issues, and existing solutions either reduce read current or increase circuit area.
Innovation Solution
The implementation of a modulated body bias voltage system, where a negative voltage is applied to the body nodes of transistors during simultaneous actuation of word lines to strengthen p-channel MOSFETs and weaken n-channel MOSFETs, reducing the likelihood of data flip errors and power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If simultaneous row access is performed in standard 6T SRAM cells during matrix vector multiplication, then computation speed is improved, but data flip errors occur leading to accuracy degradation
Solution Approach 1:
The patent applies body bias voltage modulation to change the electrical parameters of the SRAM cell transistors dynamically. By applying negative body bias voltage to the p-channel transistors and positive body bias voltage to the n-channel transistors during simultaneous row access, the patent adjusts the transistor threshold voltages and drive strengths to prevent data flip errors while maintaining computation speed.
Solution Approach 2:
The patent introduces dynamic body bias voltage control that adapts the SRAM cell characteristics based on the operating mode. During simultaneous row access for computation, the body bias voltages are dynamically adjusted to strengthen p-channel and weaken n-channel transistors, preventing data flips. During normal read/write operations, the body bias returns to standard levels, ensuring compatibility with conventional operations.
2Reliability
If body bias voltage is applied to prevent data flip errors, then data accuracy is improved, but power consumption increases
Solution Approach 1:
The patent applies body bias voltage modulation in a periodic manner, activating the non-standard body bias voltages only during simultaneous row access operations where data flip errors are likely to occur. During normal read and write operations, the body bias voltage returns to standard levels, minimizing additional power consumption while maintaining data accuracy during critical computation periods.
Solution Approach 2:
The patent dynamically changes the body bias voltage parameters based on the operation type. By modulating the body bias voltage only when needed (during simultaneous row access), the patent achieves data accuracy improvement while limiting power consumption increase to only the necessary periods, rather than continuously consuming extra power.
3Reliability
If specialized bit cell designs are used to prevent data flip errors, then data accuracy is improved, but circuit area increases
Solution Approach 1:
Instead of changing the physical structure of the SRAM bit cells, the patent changes the electrical parameters (body bias voltages) of the existing standard 6T SRAM cells. This approach prevents data flip errors during simultaneous row access while maintaining the same compact circuit area, as no additional transistors or structural modifications are required.
Solution Approach 2:
The patent makes the standard 6T SRAM cells multi-functional by adding body bias voltage control capability. The same SRAM cell structure serves both normal read/write operations and simultaneous row access computations, with the body bias voltage control providing the necessary adaptation without requiring specialized bit cell designs for different operations.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively prevents unwanted data flips during in-memory compute operations, maintaining accuracy while reducing power consumption and avoiding the need for specialized bit cell designs or reduced word line voltages.
Implementation Method 1
a voltage generator circuit configured to generate a first modulated body bias voltage applied to the first body bias voltage line, said first modulated body bias voltage having a non-negative voltage level prior to the simultaneous actuation of the plurality of word lines for the in-memory compute operation, and said first modulated body bias voltage having a negative voltage level during the simultaneous actuation of the plurality of word lines for the in-memory compute operation
Data Source
AI summary
An in-memory computation circuit includes a memory array with SRAM cells connected in rows by word lines and in columns by bit lines. Body bias nodes of the transistors in each SRAM cell are biased by a modulated body bias voltage. A row controller circuit simultaneously actuates word lines in parallel for an in-memory compute operation. A column processing circuit processes analog voltages developed on the bit lines in response to the simultaneous actuation to generate a decision output for the in-memory compute operation. A voltage generator circuit switches the modulated body bias voltage from a non-negative voltage level to a negative voltage level during the simultaneous actuation. The negative voltage level is adjusted dependent on integrated circuit process and/or temperature conditions in order to optimize protection against unwanted memory cell data flip.