PRAM Write Driver Circuit Test Mode for GST Cell Reliability
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Solution Overview
Problem
The reliability and life cycle of phase change random access memory (PRAM) cells, specifically those using germanium antimony telluride (GST) material, are difficult to evaluate effectively, as existing methods do not provide a sufficient stress condition for assessing their longevity and performance under severe environments.
Innovation Solution
A write driver circuit is designed with a test driver and mode control unit to provide an additional current as an acceleration factor, allowing for a stress test of GST cells during a short period, enabling evaluation of their life cycle and reliability by modifying the write current in test mode.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a normal write driver is used to provide standard write current, then the PRAM can perform normal write operations, but the life cycle and reliability of GST cells cannot be effectively evaluated
Solution Approach 1:
The write driver circuit is designed to perform multiple functions: normal write operations and reliability testing. The test driver can be activated to provide additional test current, allowing the same circuit to serve both operational and evaluation purposes without requiring separate dedicated test equipment.
Solution Approach 2:
The driver circuit includes dynamic control through mode control signals that can switch between normal operation mode and test mode. This allows the circuit to adapt its current output characteristics based on the operational requirement, providing standard current for normal writes and accelerated stress current for reliability testing.
2Reliability
If additional test current is provided through the test driver, then the life cycle and reliability can be evaluated under severe conditions, but the device complexity increases
Solution Approach 1:
The test driver is merged with the normal driver by sharing common components such as the PMOS transistor M2 and the bit line connection. This integration allows the test functionality to be added without requiring completely separate circuitry, thereby limiting the increase in device complexity while still enabling reliability evaluation.
3Loss of time
If accelerated current stress is applied for short period testing, then the life cycle can be evaluated quickly, but the GST cell may experience excessive current stress
Solution Approach 1:
The test driver provides excessive current beyond the normal write current to create accelerated stress conditions. This partial excessive action during the test phase allows rapid evaluation of cell reliability by simulating severe burn-in conditions, and the current is controlled to be applied only during designated test periods rather than continuously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution allows for the effective evaluation of GST cell reliability and life cycle by applying increased current stress, simulating severe conditions like burn-in, thereby enhancing the assessment of PRAM cell performance and reliability.
Implementation Method 1
The phase change of the GST occurs due to the Joule heating generated by a current applied to a cell
Data Source
AI summary
A phase change random access memory (PRAM) has a function of evaluating the lifetime and reliability of a cell in a write driver circuit. The write driver circuit of the PRAM includes a normal driver configured to provide a write current for set or reset of a phase change cell connected to a bit line, a test driver configured to share a node with the normal driver, and provide an additional current for a test to the write current through the shared node in response to a test mode control signal, and a mode control unit configured to control an operation according to the test mode by providing the test mode control signal to the test driver.