Variable Resistance Memory Device With 2MTJ Cell Structure
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Solution Overview
Problem
Variable resistance memory devices face challenges in suppressing disturbance and achieving high integration due to limitations in the magnetoresistive ratio (MR ratio) of magnetic tunnel junction (MTJ) elements, leading to issues with data read accuracy and storage capacity.
Innovation Solution
The implementation of a 2MTJ-per-cell method, where each memory cell includes two sub-memory cells with MTJ elements, allowing data read independent of the MR ratio, and a specific arrangement of bit lines and word lines to increase storage capacity without area expansion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a conventional 1MTJ-per-cell method is used, then the device structure is simpler, but the data read accuracy deteriorates due to low MR ratio
Solution Approach 1:
The patent divides a single memory cell into two sub-memory cells (first sub-memory cell with first MTJ element, second sub-memory cell with second MTJ element). This segmentation allows differential reading where the resistance difference between the two MTJ elements is measured, enabling accurate data detection even when individual MTJ elements have low MR ratios. The segmented structure converts an absolute resistance measurement problem into a differential measurement problem.
Solution Approach 2:
The patent changes the measurement parameter from absolute resistance value to resistance difference (ΔR) between two MTJ elements. By measuring the difference in resistance changes of the first and second MTJ elements, the system can detect data states accurately regardless of the absolute MR ratio of individual elements. This parameter transformation enables reliable reading even with low-MR ratio materials.
2Quantity of substance
If the storage capacity is increased by adding more memory cells, then the storage capacity improves, but the device area expands
Solution Approach 1:
The patent merges multiple functions into a single memory cell structure. Each memory cell contains two sub-memory cells that can independently store data bits. By sharing common bit lines and word lines between the two sub-memory cells, the design achieves increased storage capacity without proportional area expansion. The merged structure allows one memory cell to store multiple bits through differential encoding.
Solution Approach 2:
The first and second bit lines serve multiple functions: they are used for both writing data to and reading data from the memory cell. The same bit line infrastructure supports both the first sub-memory cell and the second sub-memory cell. This multi-functionality reduces the need for additional dedicated lines, thereby increasing storage capacity without expanding the device area proportionally.
3Measurement precision
If the MR ratio is increased to improve data read accuracy, then the data read accuracy improves, but the disturbance suppression deteriorates
Solution Approach 1:
The patent introduces bit line resistance as an intermediary factor in the measurement process. The differential measurement approach uses the bit line resistance differences caused by the two MTJ elements to extract data information. This intermediary mechanism allows accurate reading without requiring high MR ratio materials, thereby avoiding the disturbance issues that arise from using high-MR ratio materials. The bit line resistance serves as a mediator that enables detection without direct reliance on extreme material properties.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate data reading and writing with reduced disturbance, maintaining high storage capacity while minimizing the impact of low MR ratios, allowing for efficient operation and integration of variable resistance memory devices.
Implementation Method 1
a variable resistance memory device includes: a magnetic tunnel junction (MTJ) element
Data Source
AI summary
A variable resistance memory device includes plural first, second, and third conductors, plural memory cells, and a write circuit. Each memory cell is between one first conductor and one third conductor, and includes a first sub memory cell and a second sub memory cell. The first sub memory cell is between the one first conductor and one second conductor, and includes a first variable resistance element and a first bidirectional switching element. The second sub memory cell is between the one second conductor and the one third conductor, and includes a second variable resistance element and a second bidirectional switching element. The write circuit applies a first potential to the first and third conductors of a selected memory cell, a second potential to the second conductor of the selected memory cell, and a third potential to the first and third conductors of non-selected memory cells.