Pseudo SRAM Hidden Refresh Clock Segmentation
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Solution Overview
Problem
Existing pseudo static random access memory (SRAM) technologies require periodic refresh operations, which can interfere with normal data access operations and do not effectively combine the advantages of DRAM and SRAM in terms of density, speed, and chip area usage.
Innovation Solution
A hidden refresh method for pseudo SRAM that generates a refresh clock signal non-overlapping with the system clock signal, allowing refresh operations to be triggered without interfering with data access operations, and utilizing a sense amplifier enable pulse to activate the refresh operation independently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If periodic refresh operations are performed in pseudo SRAM, then data loss due to current leakage is prevented, but normal data access operations are interfered with
Solution Approach 1:
The patent implements periodic refresh operations by generating a refresh clock signal that is non-overlapping with the system clock signal. The refresh clock signal has a duty cycle of approximately 50% and is generated with a frequency that is a fraction of the system clock frequency, enabling periodic refresh without continuous interference with data access operations
Solution Approach 2:
The patent segments the clocking operations into two distinct non-overlapping phases: data access operations controlled by the system clock signal and refresh operations controlled by the refresh clock signal. This segmentation is achieved through a clock generator that produces non-overlapping clock phases, allowing both operations to occur independently without mutual interference
2Extent of automation
If refresh operations are performed during data access operations, then refresh tasks are automated, but operation complexity increases
Solution Approach 1:
The patent implements self-service automation through an on-chip refresh circuit that automatically performs refresh operations without user intervention. The refresh circuit is triggered by the refresh clock signal and autonomously manages the refresh process, freeing the user from manual refresh task management while maintaining simple SRAM-like interface operations
Solution Approach 2:
The patent introduces a clock generator as an intermediary component that coordinates between the system clock signal and refresh operations. This intermediary generates the non-overlapping refresh clock signal based on the system clock, simplifying the coordination complexity by centralizing the clock management function
3Productivity
If non-overlapping clock signals are used for refresh and data access, then operations are seamlessly integrated, but clock signal generation complexity increases
Solution Approach 1:
The clock generator employs periodic action by producing a refresh clock signal with a duty cycle of approximately 50% and a frequency that is a simple fraction of the system clock frequency. This periodic structure with non-overlapping phases enables seamless integration of refresh and data access operations while keeping the generation logic relatively simple
Data Source
AI summary
In an exemplary hidden refresh method for a pseudo SRAM, a system clock is received. A duty-on period of the system clock signal is adapted for performing a data access operation such as write or read operation. A refresh clock signal subjected to the control of the system clock signal is generated. A duty-on period of the refresh clock signal is non-overlapped with the duty-on period of the system clock signal. A refresh control pulse then is triggered by a starting edge of the duty-on period of the refresh clock signal to activate a word line, for performing a refresh operation.