Data Strobe Control Device for Low Voltage Margin
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Solution Overview
Problem
Semiconductor memory devices face operational issues in low power-supply voltage environments, particularly in plus mode, where faulty operations can occur due to margin defects between address and operation commands.
Innovation Solution
A data strobe control device is designed with a plus-mode controller, on-the-fly controller, path controller, and strobe pulse generator to manage control signals and address latching, ensuring proper operation by synchronizing signals and reducing the number of gate stages, thereby improving margin in low-voltage and high-frequency states.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a normal 4-clock base operation is performed in on-the-fly mode, then address variation occurs in the range of 4 clocks, but a clock base operation is needed for the plus on-the-fly mode requiring additional address toggle actions
Solution Approach 1:
The patent implements dynamic operation modes that can switch between 4-clock base operation and 2-clock base operation. The plus-mode controller dynamically adjusts the address toggle timing based on the selected mode, allowing the system to adapt its addressing scheme to match the operational requirements of different modes without requiring separate hardwired control paths for each mode.
Solution Approach 2:
The address toggle mechanism is designed to serve multiple functions: it handles both the normal 4-clock base operation and the plus mode 2-clock base operation using the same hardware structure. The plus-mode controller and on-the-fly controller work together to provide universal address control that adapts to different operational requirements, eliminating the need for separate address control circuits for each mode.
2Reliability
If multiple control logic stages are used to manage plus mode and on-the-fly mode, then operational control is achieved, but the number of gate stages increases reducing margin in low voltage environments
Solution Approach 1:
The patent combines the plus-mode control logic and on-the-fly control logic into an integrated control structure. The plus-mode controller and on-the-fly controller share common signal paths and control elements, merging their functions to reduce the total number of gate stages. This consolidation maintains the necessary operational control while reducing the cumulative delay that would otherwise accumulate through separate, independent control chains.
Solution Approach 2:
The patent extracts and eliminates redundant control stages from the signal path. By carefully analyzing the control requirements of plus mode and on-the-fly mode, the design removes unnecessary intermediate logic stages that do not contribute to functional control, thereby reducing the total gate depth while preserving the essential control functionality needed for reliable operation.
3Speed
If clock frequency is increased to improve operation speed, then bandwidth increases, but margin between address and operation command decreases in low power-supply voltage environments
Solution Approach 1:
The patent implements preliminary address toggling actions that occur in advance of the actual data write operation. By performing the address toggle sequence earlier in the clock cycle, the system creates a time buffer or margin between the address stabilization and the subsequent operation command execution. This preliminary timing arrangement ensures that even at high clock frequencies and low voltages, the address is fully established before the command is issued, maintaining reliable operation.
Data Source
AI summary
A data strobe control device is disclosed, which relates to a technology for controlling a data write path of a semiconductor memory device. The data strobe control device includes: a plus-mode controller configured to output a first control signal for controlling a first mode and a plus on-the-fly signal upon receiving a plus-mode signal and an on-the-fly signal; an on-the-fly controller configured to output a second control signal for controlling a second mode according to the on-the-fly signal and an operation signal; a path controller configured to latch an address in response to the second control signal during the second mode, latch the address in response to the first control signal during the first mode, and accordingly output an address latch signal; and a strobe pulse generator configured to output a strobe control signal synchronized with a control clock signal in response to the address latch signal and a burst length signal.