Variable Resistance Memory Cell Weak Set Voltage Retention
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Solution Overview
Problem
Resistance variable memory devices face challenges in achieving sufficient data retention characteristics due to the physical state of the substance forming resistance, leading to asymmetry in voltage-current characteristics and instability in memory cell states.
Innovation Solution
A non-volatile semiconductor memory device with a memory cell array featuring variable resistance elements, where a control circuit applies specific voltages to set and read data, and a weak set voltage is used to maintain the resistance state, preventing degradation and erroneous changes in the memory cell state.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If resistance variable memory is used for non-volatile storage, then three-dimensional formation is easy, but data retention characteristics are insufficient
Solution Approach 1:
The memory cell is divided into multiple functional layers: a variable resistance element layer for data storage and a charge trapping layer for state stabilization. This segmentation allows each layer to specialize in its function, with the charge trapping layer compensating for the insufficient data retention of the variable resistance element.
Solution Approach 2:
A charge trapping layer is introduced as an intermediary between the variable resistance element and the electrodes. This intermediate layer traps charges to stabilize the resistance state, thereby improving data retention without affecting the ease of three-dimensional formation of the variable resistance element.
2Ease of operation
If voltage is applied to change resistance state, then data writing is achieved, but state stability degrades over time
Solution Approach 1:
The charge trapping layer provides a feedback mechanism where trapped charges create an electric field that counteracts drift in the resistance state. This feedback stabilizes the resistance state over time by automatically compensating for degradation through charge accumulation or depletion.
Solution Approach 2:
The invention changes the electrical parameters of the memory cell by introducing a layer with different charge trapping characteristics. This parameter change allows the system to maintain stable resistance states by controlling charge distribution in the intermediate layer, thereby improving long-term stability.
3Reliability
If weak set voltage is applied continuously, then data retention is improved, but energy consumption increases
Solution Approach 1:
Instead of continuous application of weak set voltage, the system uses periodic refresh operations where the charge trapping layer is periodically recharged or reconfigured. This periodic action maintains data retention while significantly reducing average energy consumption compared to continuous voltage application.
Solution Approach 2:
The charge trapping layer provides self-service by automatically maintaining the resistance state through charge trapping and retention mechanisms. Once charges are trapped, they passively stabilize the state without requiring continuous external energy input, thereby reducing energy consumption while maintaining reliability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively enhances data retention and stability of memory cell states by applying a weak set voltage, ensuring the memory cell remains in a consistent resistance state for longer periods and reducing the likelihood of erroneous changes, thus improving the overall performance of the non-volatile semiconductor memory device.
Implementation Method 1
a variable resistance element storing data in a non-volatile manner by a resistance value
Implementation Method 2
applies to the memory cell at predetermined timing weak write voltage causing the variable resistance element to be held in the first resistance state and the second resistance state
Data Source
AI summary
A non-volatile semiconductor memory device includes a memory cell array including a first wire, a second wire crossing the first wire, and a memory cell connected to both the wires at a crossing portion of the first wire and the second wire, the memory cell including a variable resistance element storing data in a non-volatile manner by a resistance value, and a control circuit setting the variable resistance element in first or second resistance state by application of first or second voltage to the memory cell and reading data from the memory cell by application of third voltage to the memory cell. The control circuit applies to the memory cell at predetermined timing weak write voltage causing the variable resistance element to be held in the first resistance state and the second resistance state.