Software Programmable DDR Memory Interface Timing Offset Control
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Solution Overview
Problem
Controller for double data rate (DDR) memory devices faces challenges in meeting timing requirements for setup and hold of data writes and sampling of read data, particularly in generating and tuning timing offsets for strobe signals, which requires complex hardware design to avoid timing glitches.
Innovation Solution
A software programmable double data rate memory interface circuit with a digitally controllable delay element and characterization circuitry allows for software-controlled timing offset adjustments, eliminating the need for complex hardware design and ensuring stable transactions by temporarily holding off data transfers during setting updates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a completely autonomous hardware mechanism is used to adjust delay settings, then the system can automatically compensate for timing variations, but the design becomes complex and may cause timing glitches during transactions
Solution Approach 1:
The patent replaces the autonomous hardware delay adjustment mechanism with a software-controlled system. The software programmable delay element is configured and adjusted through software, eliminating the need for complex hardware automatic adjustment circuitry while maintaining timing stability and avoiding timing glitches during transactions.
Solution Approach 2:
The patent introduces software as an intermediary between the user and the delay adjustment mechanism. Instead of direct hardware control, software acts as the mediator to program and adjust delay settings, simplifying the overall system design while providing flexible control over timing parameters.
2Extent of automation
If autonomous hardware adjustment is implemented, then timing compensation is automatic, but timing glitches may occur when delay settings are altered during transactions
Solution Approach 1:
The patent substitutes autonomous hardware adjustment with software-controlled adjustment. The software programmable delay element allows timing compensation to be performed through software commands, enabling automatic adjustment while preventing timing glitches by controlling when adjustments occur through software logic rather than autonomous hardware operation.
Solution Approach 2:
The patent implements preliminary action by having the software hold off data transfers momentarily before applying delay setting changes. This ensures that timing adjustments are made during safe periods when no transactions are active, preventing timing glitches and maintaining transaction stability.
3Adaptability or versatility
If hardware-based delay adjustment is used, then timing offsets can be tuned, but the design requires careful engineering to avoid glitches
Solution Approach 1:
The patent replaces hardware-based delay adjustment with software-based adjustment. The software programmable delay element provides the same delay tuning capability but through software configuration, eliminating the need for careful hardware design and reducing overall system complexity while maintaining adaptability.
4Device complexity
If software-controlled delay adjustment is implemented, then design is simplified, but the mechanism must hold off transactions during updates
Solution Approach 1:
The patent applies preliminary action by having the software hold off data transfers momentarily before applying delay setting changes. This brief pause ensures safe adjustment of the software programmable delay element without interfering with active transactions, maintaining design simplicity while minimizing time loss.
Solution Approach 2:
The patent uses the skipping principle by making the transaction pause as brief as possible. The software quickly holds off transactions only long enough to safely update the delay setting, then resumes normal operation, minimizing the impact on overall system performance while maintaining design simplicity.
Data Source
AI summary
A double data rate memory interface circuit for transferring data between an interfacing device and double data rate memory device. The interface circuit comprises a data input for receiving a data signal from a first of those devices, and a strobe input for receiving a strobe signal from that first device. The interface circuit also comprises delay circuitry for supplying the data and strobe signals to the other device with a timing offset introduced therebetween. The delay circuitry comprises a software programmable storage medium and a digitally controllable delay element coupled to the storage medium, the delay element being arranged to control the timing offset in dependence on a delay setting programmed into that storage medium.