Semiconductor Memory Device Hidden Write Control Circuit
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Solution Overview
Problem
Conventional semiconductor memory devices require increased test initialization time due to separate dummy CBR refresh and dummy write operations, which are necessary to account for initial test failures in devices using recess channel array transistors.
Innovation Solution
The integration of a hidden write operation using the CBR refresh command, where all memory cells connected to a common bit line can write data simultaneously, reducing the need for separate dummy operations and thus shortening the test initialization time.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If separate dummy CBR refresh and dummy write operations are performed during test initialization, then initial test failures are accounted for, but test initialization time increases
Solution Approach 1:
The patent combines the dummy CBR refresh operation and dummy write operation into a single integrated operation. During test initialization, when a CBR refresh command is issued, the system simultaneously performs the refresh function and executes a hidden write operation to all memory cells through bit line selection, eliminating the need for separate dummy operations while ensuring all memory cells are properly exercised before actual testing begins
2Reliability
If only one memory cell writes data at a time during dummy write operation, then write operation is performed, but test initialization time increases
Solution Approach 1:
The patent transitions from sequential single-cell writing to parallel multi-cell writing by utilizing the bit line dimension. When a CBR refresh command is issued, the column decoder selects all bit lines simultaneously, enabling all memory cells connected to these bit lines to perform write operations in parallel during the same time period, thereby dramatically increasing test initialization speed
Data Source
AI summary
A semiconductor memory device and its operating method are disclosed. The semiconductor memory device includes; a memory cell array including a plurality of memory cells selected in relation to a plurality of word lines and a plurality of bit lines, an address decoder selecting at least one word line in response to a refresh address and selecting all of the plurality of bit lines in response to a hidden write signal when a CBR refresh operation is requested during a test mode, a hidden write control circuit generating the hidden write signal when the CBR refresh operation is requested during the test mode, a refresh address generating circuit generating the refresh address when the CBR refresh operation is requested during the test mode, and a data input circuit applying data to all of the plurality of bit lines when the CBR refresh operation is requested during the test mode.