Ingress Data Placement Logic for I/O Adapter Latency Reduction
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Solution Overview
Problem
Server computers face latency issues when processing data requests due to additional processing performed by I/O adapter devices, which can delay the transfer of data from storage locations to host devices.
Innovation Solution
Implementing specialized ingress data placement logic in I/O adapter devices to bypass the processor and directly transfer data from storage locations to host devices, using content addressable memory (CAM) units to manage and route response packets efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If data is transferred through the I/O adapter processor for management and handling, then data processing capability is improved, but latency increases
Solution Approach 1:
The patent segments the data transfer path into two separate paths: a high-latency path through the I/O adapter processor for complex data management tasks, and a low-latency path that bypasses the processor for straightforward data transfers. This segmentation allows the system to handle different types of data transfers with appropriate processing levels, improving overall efficiency while maintaining necessary processing capability for complex operations.
Solution Approach 2:
The patent introduces an intermediary mechanism (the ingress data placement logic and associated data structures) that enables direct data placement without requiring full processor intervention. This intermediary layer handles the coordination between storage locations and host devices, allowing data to flow through a faster path while still maintaining system control and management capabilities.
2Adaptability or versatility
If I/O adapter processor manages all I/O transactions, then data routing flexibility is improved, but processing speed decreases
Solution Approach 1:
The patent implements preliminary action by pre-configuring data structures and routing information in advance. The system prepares data placement information, routing tables, and buffer configurations before actual data transfer occurs. This allows the low-latency path to execute quickly without requiring real-time processor decisions, maintaining routing flexibility through pre-computed configurations while achieving high processing speed during actual data transfer.
Solution Approach 2:
The patent enables self-service by allowing the data transfer system to autonomously route and place data without continuous processor intervention. The ingress data placement logic and associated data structures enable the system to automatically match data with appropriate buffers and destinations, maintaining routing flexibility through intelligent algorithms while achieving high speed through automated, processor-independent execution.
3Loss of time
If direct data transfer path is used, then latency is reduced, but processor control capability is diminished
Solution Approach 1:
The patent implements feedback mechanisms where the results of direct data transfers are reported back to the processor for verification and future optimization. The system monitors data transfer outcomes, buffer utilization, and routing effectiveness, using this feedback to refine routing algorithms and data structure configurations. This maintains processor control capability through iterative improvement while preserving the low-latency benefits of direct transfer paths.
Solution Approach 2:
The patent replaces the mechanical processor intervention model with an automated software-based control system. Instead of requiring the processor to physically manage each data transfer operation, the system uses programmed logic, data structures, and algorithms to automate the control functions. This substitution maintains processor control capability through software intelligence while eliminating the latency associated with processor intervention.
Data Source
AI summary
Server computers often include one or more input/output (I/O) devices for communicating with a network or directly attached storage device. The data transfer latency for request can be reduced by utilizing ingress data placement logic to bypass the processor of the I/O device. For example, host memory descriptors can be stored in a memory of the I/O device to facilitate placement of the requested data.