Memory System With Different Latencies Sharing Common Bus
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Solution Overview
Problem
Conventional memory systems face challenges in increasing data transfer size without expanding the number of lines or commands between the controller and memory devices, which can lead to increased error correction needs and costly system redesigns.
Innovation Solution
Implementing a memory system where multiple memory devices share a common data bus and control bus, with each device having different latencies set to match a data burst length, allowing for simultaneous data transfer and error correction through additive latency adjustments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of data bus is increased to transfer larger data, then error correction capability is improved, but manufacturing cost increases significantly
Solution Approach 1:
The patent merges multiple memory devices into a single memory system that shares common data bus and control bus. By coordinating operations across multiple devices with different latencies, the system achieves enhanced error correction capability through increased data transfer size without requiring a larger physical data bus, thereby avoiding significant manufacturing cost increases
2Reliability
If the number of commands applied to memory devices is increased to transfer larger data, then error correction capability is improved, but device complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-configuring different additive latencies for each memory device. This allows the controller to issue a single command that triggers coordinated data transfer across multiple devices with different latencies, eliminating the need for multiple separate commands while achieving enhanced error correction capability
3Ease of manufacture
If multiple memory devices share common buses, then ease of manufacture is improved, but device complexity increases due to latency coordination
Solution Approach 1:
The patent changes the latency parameter of each memory device by configuring different additive latencies. This parameter differentiation allows the system to coordinate data transfer timing across multiple devices sharing common buses, resolving timing conflicts and enabling seamless operation while maintaining cost-effectiveness through shared hardware resources
Data Source
AI summary
A memory system includes memory devices sharing a data bus and a control bus and controlling the memory devices through the control bus, wherein the memory devices have different latencies each other, and a controller transceiving a data with the memory devices through the data bus, wherein the controller may transceive a data with the memory devices during a time corresponding to a data burst length for a moment being the each latencies of the memory devices after transmitting same control signals to the memory devices.