9T Bitcell pFET Header for Low Voltage Write Speed
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Solution Overview
Problem
Low voltage operation in sub 65-nm processors leads to increased device variations, leakage, and threshold voltage sensitivity, resulting in reduced yield and performance issues, particularly in low voltage memory arrays where write speed is limited by pFET weakness and exponential performance degradation as supply voltage approaches threshold voltage.
Innovation Solution
The introduction of a nine transistor (9T) bitcell design with a pFET header and optional nFET footer, which decouples nFET-pFET contention, allowing for faster write speeds and improved data retention by controlling the pFET header to reduce contention and leakage, enabling efficient low voltage operation without compromising noise margins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional 8T bitcell is used for low voltage operation, then power consumption is reduced, but write speed deteriorates due to pFET weakness and increased device variations
Solution Approach 1:
The bitcell is segmented into distinct functional regions with specialized transistors: header pFETs for rapid voltage transition, nFET pass transistors for data input, and footer pFETs for leakage control. This segmentation allows each component to be optimized for its specific function, resolving the contradiction between low power and high write speed.
Solution Approach 2:
Different transistor types and configurations are applied to different locations within the bitcell: pFET headers at the top for fast charging, nFET pass transistors in the middle for data control, and pFET footers at the bottom for leakage prevention. This local differentiation enables simultaneous optimization of speed and power characteristics.
2Use of energy by moving object
If supply voltage is reduced for low voltage operation, then power consumption decreases, but performance degrades exponentially as voltage approaches threshold voltage
Solution Approach 1:
The bitcell operates with supply voltages in the range of 0.5V to 1.2V, significantly below conventional voltages. The header pFETs are specifically designed to provide sufficient drive strength at these reduced voltages, enabling fast write operations while maintaining low power consumption and stable performance.
Solution Approach 2:
The header pFETs are pre-positioned and pre-biased to be ready for rapid activation. When a write operation is needed, the header pFETs can immediately begin charging the bitline to the full supply voltage, ensuring fast write speed even at low operating voltages before the actual data write occurs.
3Device complexity
If pFET-nFET contention is present in conventional bitcells, then circuit complexity is reduced, but leakage increases and write speed decreases
Solution Approach 1:
The footer pFETs are extracted from the conventional 8T bitcell structure and added as separate leakage control elements. These footer pFETs are specifically dedicated to blocking leakage paths during standby mode, allowing the main nFET-pFET inverters to maintain simple structure while the footers handle the leakage control function.
Solution Approach 2:
The footer pFETs act as intermediary elements between the nFET pass transistors and ground. They provide a controlled path that prevents direct leakage from the bitline to ground while still allowing proper discharge during write operations, thus mediating between leakage prevention and write speed requirements.
Data Source
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AI summary
In low power CPUs, the best way to reduce power is to reduce supply voltage. Most low voltage memory arrays use an 8T cell (450), which has read stability immunity, in order to operate at low voltages. An embodiment of the disclosure determines when a write wordline (WWL 410) rises. If the determination (header pFET 430) shows that the WWL has risen, at least one of the plurality of p-channel field effect transistors (pFETS 432, 434) is disconnected from a voltage supply, and the at least one plurality of n-channel field effect transistors (nFET) pass gate transistors (440, 442) are opened.