Memory Device Calibration Data Storage and Compensation
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Solution Overview
Problem
Memory devices manufactured through semiconductor processes exhibit variations due to factors like process, voltage, temperature, and aging, which affect data reading and require calibration to ensure accurate data retrieval.
Innovation Solution
A memory device with a cell array comprising two sections that share word lines, each section storing calibration data and its inverted bits, utilizing column decoders and a read circuit to compare outputs and generate calibration data for compensating variations, allowing for efficient calibration and reliable data storage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If calibration data is stored in separate non-volatile storage, then reliability of calibration data is improved, but device complexity increases
Solution Approach 1:
The patent merges the calibration data storage function with the main memory cell array by storing calibration data in the same volatile memory cells that store user data. This eliminates the need for separate non-volatile storage components, thereby reducing device complexity while maintaining calibration functionality through the use of inverted bit storage in corresponding memory locations.
Solution Approach 2:
The memory cell array is designed to serve multiple functions: it stores both user data and calibration data in the same physical storage locations. The same memory cells, word lines, and bit lines are used for both regular memory operations and calibration operations, eliminating the need for dedicated separate storage hardware and reducing overall device complexity.
2Device complexity
If calibration data is stored in the same memory cells as user data, then device structure is simplified, but data accuracy may be affected by variations
Solution Approach 1:
The patent segments the memory array into two functional sections: a first section for storing user data and a second section for storing inverted calibration data. Both sections share the same physical memory cells, word lines, and bit lines, but are logically separated through address decoding. This segmentation allows accurate differentiation between user data and calibration data while using the same physical storage infrastructure.
Solution Approach 2:
The patent stores inverted bits of calibration data in the second section of the memory array. By inverting the calibration data bits and storing them in corresponding memory locations, the system can accurately retrieve calibration information even when subject to the same process, voltage, and temperature variations that affect user data storage, thereby maintaining data accuracy.
3Measurement precision
If inverted bits of calibration data are stored in corresponding memory locations, then compensation accuracy is improved, but write operation complexity increases
Solution Approach 1:
The patent employs a self-service mechanism where the memory system automatically generates and stores inverted calibration data during the calibration process. The same memory cells and control circuits that store user data are used to store the inverted calibration data, eliminating the need for separate hardware or complex external processing to generate inverted bits.
Solution Approach 2:
The patent changes the state parameter of calibration data by inverting the bits (changing 0s to 1s and 1s to 0s) before storing them in the second section. This parameter transformation allows the system to compensate for variations more accurately during read operations, as the inverted bits provide a reference that counteracts the effects of process, voltage, and temperature variations.
4Measurement precision
If separate column decoders are used for first and second sections, then data retrieval accuracy is improved, but device complexity increases
Solution Approach 1:
The patent segments the column decoding function into two separate column decoders: a first column decoder for decoding addresses of user data in the first section, and a second column decoder for decoding addresses of inverted calibration data in the second section. This segmentation allows each decoder to be optimized for its specific function, improving data retrieval accuracy while maintaining manageable complexity through functional specialization.
Data Source
AI summary
A memory device may include a cell array including a first section and a second section that share a plurality of word lines comprising a first set of word lines and a second set of word lines, a first column decoder configured to select at least one bit line of a first set of bit lines connected to the first section, a second column decoder configured to select at least one bit line of a second set of bit lines connected to the second section, and a read circuit configured to output a data signal based on a comparison between an output of the first column decoder and an output of the second column decoder. The first section includes a plurality of first memory cells connected to at least one word line from the first set of word lines and configured to store bits of calibration data for calibrating the memory device, and the second section includes a plurality of second memory cells connected to the at least one word line and configured to store inverted bits of the calibration data.