4T-SRAM Cell Leakage Reduction via Floating Node Asymmetry
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Solution Overview
Problem
Conventional 6T SRAM cells occupy large silicon area, leading to high fabrication costs and significant leakage current, making them less efficient for high-density memory storage and fast data access required by modern computer processors.
Innovation Solution
The 4T SRAM cell design uses two p-type MOSFET devices for data storage and two n-type MOSFET devices as access switches, eliminating low voltage node VSS, which allows for a write circuit to set storage nodes to high and ground voltage simultaneously and a read circuit to detect asymmetrical voltage differences, reducing leakage current and preventing false readings.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional 6T SRAM cell structure is used, then data storage reliability is maintained, but silicon area occupation increases leading to high fabrication cost
Solution Approach 1:
The patent removes two transistors (specifically the pull-down NFET devices) from the conventional 6T SRAM cell structure, extracting only the essential components needed for data storage and access. This reduction from 6T to 4T configuration directly decreases silicon area occupation while maintaining core functionality, thereby lowering fabrication cost per-bit-storage.
Solution Approach 2:
The patent changes the voltage biasing parameters by eliminating the need for one storage node to be continuously biased at ground voltage (VSS). By allowing storage nodes to float and using asymmetrical voltage detection during read operations, the design achieves area reduction without sacrificing data retention reliability.
2Loss of energy
If conventional 6T SRAM cell structure is used, then data storage stability is maintained, but leakage current increases
Solution Approach 1:
The patent converts the potential harm of floating storage nodes (which could lead to unstable voltage levels) into a benefit by implementing asymmetrical voltage detection during read operations. The floating nodes naturally drift to intermediate voltage levels, and this characteristic is exploited through differential sensing to detect stored data while maintaining low leakage current.
Solution Approach 2:
Instead of actively maintaining storage nodes at fixed voltage rails (VDD or VSS) through continuous transistor biasing, the patent inverts the approach by allowing nodes to float and detecting data through voltage differences relative to bitline levels. This inversion reduces transistor switching activity and associated leakage while preserving data stability.
3Area of stationary object
If 4T SRAM cell structure is used, then silicon area is reduced, but write operation complexity increases due to floating storage nodes
Solution Approach 1:
The write circuit performs preliminary actions by pre-charging bitlines to appropriate voltage levels (VDD or VSS) before activating access transistors. This preliminary preparation ensures that when the write operation begins, the voltage differential is already established, simplifying the actual data writing process despite the floating storage node configuration.
Solution Approach 2:
The patent introduces bitlines and complementary bitlines as intermediary elements that mediate between the write circuit and floating storage nodes. These intermediaries buffer and condition the write signals, isolating the complexity of floating node management from the core write operation and enabling simpler write circuit design.
4Ease of manufacture
If 4T SRAM cell structure is used, then fabrication cost is reduced, but read operation accuracy may be affected by residual charges
Solution Approach 1:
The read operation employs periodic action through sequential steps: first discharging residual charges from bitlines, then performing the actual read detection. This periodic reset and detect sequence ensures that residual charges from previous operations do not interfere with current read accuracy, while maintaining the cost benefits of the 4T structure.
Solution Approach 2:
The patent applies preliminary anti-action by actively discharging residual charges on bitlines before read operations. This preventive measure counteracts the potential harmful effect of residual charges that could cause false readings, ensuring measurement precision is maintained despite the simplified 4T cell structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The 4T SRAM cell achieves a 25-35% reduction in size and lower fabrication costs per-bit-storage, with significantly reduced leakage current, enabling higher memory density and faster data access compatible with high-frequency computing speeds.
Implementation Method 1
two p-type Metal Oxide Semiconductor Field Effect Transistor (MOSFET) devices (201, 202 in FIG. 2) for data storage and two n-type MOSFET devices (203, 204 in FIG. 2) for access switches
Implementation Method 2
4T-SRAM has only N-drain/P-substrate (access NFET transistor 203/204) and P-drain/N-well (storage node) junction leakage currents
Data Source
AI summary
A memory device is disclosed, comprising a 4T-SRAM cell and a read circuit. The 4T-SRAM cell comprising two P-type MOSFET devices for a data bit storage and two N-type MOSFET for accessing switches has benefits of less numbers of MOSFET devices for smaller cell size and low leakage current than the conventional 6T-SRAM cell. The read circuit comprises a latch and a discharge device. The latch with two output nodes is coupled between a supply voltage rail and a ground voltage rail. The discharge device is coupled to the two output nodes, a bit line pair and the ground voltage rail. Since one of two storage nodes for the 4T-SRAM cell is floating, the stored data in the 4T-SRAM cell is vulnerable for conventional read operations. The read circuit of the invention resolves the vulnerability issue of the 4T-SRAM cell.