SRAM Bit Cells with Current Mirror-Gated Read Ports
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Solution Overview
Problem
Conventional SRAM data arrays require significant time, area, and power to perform matrix multiplication operations, as they necessitate sensing data and transferring it to a separate multiplication circuit, which is inefficient.
Innovation Solution
The implementation of SRAM bit cells with current mirror-gated read ports allows for direct multiplication within the SRAM cells by using a current mirror circuit to control the flow of current based on the stored data, enabling multiple SRAM bit cells to perform matrix multiplication with reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional SRAM data arrays are used with separate multiplication circuits, then matrix multiplication operations can be performed, but significant time, area, and power are consumed
Solution Approach 1:
The patent merges the multiplication circuit functionality directly into the SRAM bit cell structure by adding a read port with a first transistor whose gate is controlled by a current mirror circuit. This integration eliminates the need for separate multiplication circuits and sense amplifiers, allowing matrix multiplication to be performed directly within the SRAM array during read operations, thereby reducing power consumption while maintaining operational speed
2Productivity
If data is sensed and transferred to a separate multiplication circuit, then matrix multiplication can be performed, but significant area is required
Solution Approach 1:
The invention combines the multiplication functionality with the SRAM storage structure by integrating a read port that includes a current mirror-controlled transistor directly into each bit cell. This eliminates the need for separate multiplication circuits and data transfer pathways, significantly reducing the overall circuit area while preserving full matrix multiplication capability
Solution Approach 2:
The SRAM bit cell is designed to perform multiple functions: data storage, data reading, and matrix multiplication operation. The read port structure with current mirror control enables the same hardware to serve both as memory and as a computational unit, eliminating redundant components and reducing total area
3Ease of operation
If conventional read ports are used, then data can be read from SRAM bit cells, but power consumption is high
Solution Approach 1:
The patent modifies the read port parameters by introducing a current mirror circuit that controls the gate voltage of the first transistor. This allows dynamic adjustment of the read current based on the stored data value, enabling the read operation to consume minimal power when unnecessary while maintaining full reading capability when needed
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables matrix multiplication with less time, area, and power consumption compared to conventional systems, as the SRAM bit cells can perform multiplication operations internally, eliminating the need for separate multiplication circuits and reducing overall energy usage.
Implementation Method 1
a level of current that flows through the first transistor in response to a voltage applied to the gate node by the current mirror circuit correlates to a magnitude of the voltage
Implementation Method 2
cross-coupled inverters configured to store a binary data value
Implementation Method 3
a voltage applied to the first node of the second transistor to generate a current that flows to the first transistor if the second transistor is activated
Data Source
AI summary
Static random access memory (SRAM) bit cells employing current mirror-gated read ports for reduced power consumption are disclosed. In one aspect, an SRAM bit cell includes a read port employing a first transistor electrically coupled to a current sum line and to a current mirror circuit. A level of current that flows through the first transistor in response to voltage applied by the current mirror circuit correlates to a magnitude of the voltage. The read port includes a second transistor electrically coupled to the first transistor, to a driver circuit, and to an output node of a first inverter. Connecting the first and second transistors of the read port in this manner allows a voltage applied to the second transistor to generate a current that flows to the first transistor if the second transistor is activated. The current level depends on the voltage applied by the current mirror circuit.