Wordline Voltage Control for Memory Access Disturb Margin
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Solution Overview
Problem
As memory circuit elements shrink and operating voltages decrease to reduce power consumption, the access disturb margin in memory circuits increases, leading to incorrect data reads due to charge sharing between bit lines and internal nodes, causing stability issues in bit cells.
Innovation Solution
A memory circuit with a word line driver circuitry that controls the word line voltage by stepping through intermediate and high conductance levels, reducing access disturbance by managing the conductance of the word line transistor during read and write accesses, thereby enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the word line voltage is stepped through intermediate and high conductance levels during access, then the access disturbance margin is improved and data stability is enhanced, but the device complexity increases due to the need for additional word line driver circuitry to control the voltage transitions
Solution Approach 1:
The word line voltage is made dynamic by stepping through multiple conductance levels (low, intermediate, high) during different phases of the access operation. The word line driver circuitry dynamically adjusts the voltage levels based on the operational phase - transitioning from low conductance during idle periods, to intermediate during setup, to high during data transfer, and back to low during hold periods. This dynamic adjustment resolves the contradiction by improving data stability through controlled voltage transitions while managing the added complexity through phased operation.
Solution Approach 2:
The word line voltage control implements periodic action by cycling through different voltage levels in a repeating pattern: low voltage during idle periods, intermediate voltage during setup phase, high voltage during data transfer phase, and back to low voltage during hold period. This periodic switching of voltage levels allows the system to maintain data stability during critical operations while reducing power consumption and managing circuit complexity through rhythmic operation cycles.
2Use of energy by moving object
If the operating voltage of the memory is reduced to reduce power consumption, then energy efficiency is improved, but the access disturb margin deteriorates leading to incorrect data reads
Solution Approach 1:
The invention changes the voltage parameter dynamically during different operational phases rather than maintaining a constant low operating voltage. By stepping the word line voltage through intermediate and high levels during read operations, the system compensates for the reduced operating voltage, maintaining sufficient voltage headroom to prevent charge sharing effects and ensure accurate data reads even at lower operating voltages that reduce power consumption.
Solution Approach 2:
The word line driver circuitry performs preliminary action by transitioning the word line voltage to intermediate levels before the main data transfer operation. This preliminary voltage adjustment prepares the bit cell and surrounding circuitry for the upcoming read operation, reducing the voltage step required during actual data transfer and thereby minimizing charge sharing effects and improving access disturb margin at reduced operating voltages.
Data Source
AI summary
A memory circuit 2 includes bit cells 4 selected for reading with a word line voltage upon a word line 20. Word line voltage control circuitry 26 generates a two-step word line voltage signal. The word line voltage first increases to an intermediate level at which word line transistors 12 weakly couple the bit cell 4 to the bit lines 8. This intermediate level is maintained for a first delay period. After the first delay period, the word line voltage is increased to a full rail value and this full rail value maintained for a second delay period. The word line voltage is then returned to a low level at the end of the read operation. This two-step word line voltage signal provides a better access disturb margin for the bit cell 4.