Two Capacitor Self-Referencing Nonvolatile Bitcell for Zero Leakage
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing portable electronic devices face challenges in reducing leakage current during standby power mode, requiring continuous power to retain state information, which is inefficient for battery-operated devices and energy harvesting applications.
Innovation Solution
The implementation of nonvolatile logic (NVL) using ferroelectric capacitors in a System on Chip (SoC) architecture, allowing complete power removal without data loss, with NVL arrays dispersing throughout the logic cloud to save and restore flip-flop states efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If continuous power is provided to retain state information in standby mode, then data retention is maintained, but leakage current increases and energy consumption rises
Solution Approach 1:
The patent applies preliminary action by capturing and storing the state information of logic elements into nonvolatile memory cells before the device enters standby mode. This pre-storing of state data allows the system to completely power down logic circuits during standby while preserving state information, eliminating leakage current entirely. The nonvolatile memory cells retain the captured state without requiring any power, and the state is automatically restored upon power-up.
2Loss of energy
If power is completely removed during standby mode, then leakage current is eliminated, but state information is lost
Solution Approach 1:
The patent introduces nonvolatile memory cells as an intermediary between the logic circuits and power supply. These memory cells serve as a mediator that captures state information from logic elements when powered, then maintains this information without power during standby mode. The intermediary nonvolatile memory cells effectively decouple the logic circuits from continuous power requirements, allowing complete power removal while preserving state data through the intermediary storage mechanism.
3Reliability
If shadow latch is added to retain state in master-slave flip-flop, then data retention during power-down is improved, but device complexity increases
Solution Approach 1:
The patent applies segmentation by separating the state retention function from the logic elements themselves. Instead of modifying each logic element with complex retention circuits, the system divides functionality by using dedicated nonvolatile memory cells for state storage. This segmentation allows logic circuits to be simple and power-efficient, while state retention is handled independently by the nonvolatile memory segment, reducing overall device complexity compared to integrated retention circuits.
4Use of energy by moving object
If energy harvesting is used to power the device, then power efficiency is improved, but the small amount of harvested power is insufficient for continuous operation
Solution Approach 1:
The patent enables periodic action by allowing the device to operate in cycles of active mode and complete power-down mode. Energy harvested during active operation is sufficient to power the nonvolatile memory cells for state capture and retention. During standby, the device enters complete power-down with zero consumption, then rapidly restores state upon power-up. This periodic operation pattern matches the intermittent nature of energy harvesting, accumulating energy when available and conserving it through complete power-off periods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables zero leakage in sleep mode and rapid system state restoration, reducing energy consumption and eliminating the need for constant power sources, ideal for energy harvesting applications and handheld devices with limited resources.
Implementation Method 1
Two capacitor self-referencing nonvolatile bitcell... Each bit cell includes two ferroelectric capacitors connected in series
Data Source
AI summary
A system on chip (SoC) provides a memory array of self referencing nonvolatile bitcells. Each bit cell includes two ferroelectric capacitors connected in series between a first plate line and a second plate line, such that a node Q is formed between the two ferroelectric capacitors. The first plate line and the second plate line are configured to provide a voltage approximately equal to first voltage while the bit cell is not being accessed. A clamping circuit coupled to the node Q. A first read capacitor is coupled to the bit line via a transfer device controlled by a first control signal. A second read capacitor coupled to the bit line via another transfer device controlled by a second control signal. A sense amp is coupled between the first read capacitor and the second read capacitor.