Charge Sharing CIM Bit Cell for Energy Efficient MAC Operations
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Solution Overview
Problem
Current computing systems face bottlenecks in data transfer between memory and processing elements, leading to inefficiencies in data retrieval and storage, especially as data sets grow, due to the need for large data capacities and proximity to processing nodes, resulting in high energy consumption and reduced computational throughput.
Innovation Solution
The implementation of Compute-In-Memory (CIM) bit cell circuits that perform operations locally within memory arrays, using charge sharing and capacitors to eliminate the need for dedicated write ports and reduce data movement, enabling MAC operations within memory cells without transferring data to a host processor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If data is stored in separate memory from processing elements, then data storage capacity is improved, but data transfer time and energy consumption increase significantly
Solution Approach 1:
The patent merges memory storage and processing functions into a single integrated structure where memory cells perform MAC operations directly. The bit cell circuit combines storage elements with computational logic, eliminating the need for separate memory and processing units, thus reducing data transfer energy while maintaining large storage capacity
Solution Approach 2:
The patent introduces capacitors as intermediary elements that enable charge sharing between memory cells during computational operations. These capacitors facilitate local data processing within the memory array without requiring data to be transferred to external processing units, reducing energy consumption for data movement
2Quantity of substance
If data is stored in separate memory from processing elements, then data storage capacity is improved, but computational throughput decreases due to data transfer bottlenecks
Solution Approach 1:
The patent combines memory and computation functions within the same physical structure, allowing MAC operations to be performed directly on stored data. This integration eliminates data transfer bottlenecks while maintaining large storage capacity, thereby improving computational throughput
Solution Approach 2:
The patent performs computational operations directly at the memory location where data is stored, rather than first transferring data to processing units. This preliminary action of computing in-place eliminates the time-consuming data transfer step, improving overall computational throughput
3Device complexity
If conventional memory architectures are used, then data storage is simplified, but dedicated write ports and data movement are required
Solution Approach 1:
The patent makes memory cells multi-functional by enabling them to perform both storage and computational operations. The same memory structure that stores data also executes MAC operations, eliminating the need for separate write ports and data movement mechanisms while maintaining architectural simplicity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces energy consumption and increases memory bandwidth, allowing for higher throughput in computations by performing operations like dot-products and absolute differences locally within memory cells, thereby accelerating algorithm execution and reducing overall energy use.
Implementation Method 1
a capacitor coupled between the bit cell output and a read bit line
Implementation Method 2
charge sharing compute in memory (CIM) bit cells
Data Source
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AI summary
A charge sharing Compute In Memory (CIM) may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a system voltage. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal capacitor between the XNOR output node and a read bit line. Alternatively, a charge sharing CIM may comprise an XNOR bit cell with an internal cap between XNOR and read bit line with a separate write bit line and write bit line bar.