3D Semiconductor Device Thermal Management via Conductive Layers

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Solution Overview

Problem

Three-dimensional integrated circuits (3D ICs) face challenges in heat removal due to the poor thermal conductivity of materials like silicon dioxide and mono-crystalline silicon, leading to increased thermal resistance and difficulties in transferring heat from higher layers to the heat sink.

Innovation Solution

The integration of thermally conductive layers and materials, such as copper, aluminum, or graphene, within the 3D stack, along with the use of thermal contacts and through-layer vias, helps in enhancing heat removal by reducing thermal resistance and improving mechanical stability.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If traditional materials like silicon dioxide and mono-crystalline silicon are used in 3D IC stacks, then device integration is achieved, but thermal resistance increases and heat removal becomes difficult

Engineering Contradiction:
Improve3D IC integrationVSAvoidthermal resistance
Core Design Contradiction:
Device complexityVSTemperature

Solution Approach 1:

The patent applies composite materials by integrating thermally conductive layers (such as diamond, cubic boron nitride, or metal interconnects) within the 3D IC stack alongside traditional semiconductor materials. This composite structure combines the electrical functionality of silicon-based materials with the superior thermal conductivity of specialized materials, enabling effective heat removal while maintaining device integration.

Inventive Principle:
Principle #40Composite materials

Solution Approach 2:

The patent introduces thermally conductive intermediary layers between different device layers and heat sink structures. These intermediary layers act as thermal mediators, facilitating heat transfer from the high-power density regions in upper layers to the heat sink in lower layers, thereby reducing overall thermal resistance in the 3D stack.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If multiple layers are stacked to increase integration density, then productivity improves, but heat transfer from higher layers to heat sink becomes more difficult

Engineering Contradiction:
Improveintegration densityVSAvoidheat transfer efficiency
Core Design Contradiction:
ProductivityVSLoss of energy

Solution Approach 1:

The patent addresses heat transfer challenges in vertically stacked structures by introducing lateral thermal conduction paths through thermally conductive layers that extend across multiple device layers. This dimensional approach creates additional thermal pathways that bypass the vertical heat transfer bottleneck, enabling efficient heat removal from higher layers to the heat sink while maintaining high integration density.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent employs composite material structures with alternating layers of semiconductor materials and thermally conductive materials. This composite architecture maintains the vertical stacking for high integration density while providing continuous thermal pathways through the thermally conductive layers, solving the heat transfer efficiency problem in multi-layer configurations.

Inventive Principle:
Principle #40Composite materials

3Temperature

If thermally conductive materials are added to improve heat removal, then thermal resistance decreases, but device complexity increases

Engineering Contradiction:
Improvethermal resistanceVSAvoidstructure complexity
Core Design Contradiction:
TemperatureVSDevice complexity

Solution Approach 1:

The patent applies multi-functionality by designing metal interconnect layers that serve dual purposes: electrical connectivity between devices and thermal conduction pathways. This universal approach allows existing interconnect structures to fulfill both their traditional electrical function and an additional thermal management function, reducing the need for separate thermal conduction structures and thereby limiting the increase in device complexity.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Solution Approach 2:

The patent merges thermal management functionality with existing device structures by integrating thermally conductive materials into interconnect layers and device substrates. This merging approach combines heat removal functionality with structural and electrical components already present in the 3D IC, avoiding the need for separate dedicated thermal management structures and thus minimizing the increase in overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively reduces thermal resistance, enables efficient heat transfer from transistors to the heat removal apparatus, and provides mechanical stability, allowing for the cooling of higher power 3D-ICs while maintaining desirable temperature levels for all components.

Implementation Method 1

The integration of thermally conductive layers and materials, such as copper, aluminum, or graphene, within the 3D stack, along with the use of thermal contacts and through-layer vias, helps in enhancing heat removal by reducing thermal resistance

Methodology Applied
Scientific EffectThermal conduction: Conduction (thermal)

Implementation Method 2

enables efficient heat transfer from transistors to the heat removal apparatus, and provides mechanical stability, allowing for the cooling of higher power 3D-ICs while maintaining desirable temperature levels for all components

Methodology Applied
Scientific EffectHeat sink: Heat Sink

Data Source

PatentUS11121021B23D semiconductor device and structure
Publication Date: 2021.09.14 MONOLITHIC 3D INC
  • US11121021B2 patent drawing
  • US11121021B2 patent drawing
  • US11121021B2 patent drawing

AI summary

A 3D semiconductor device, including: a first level including a single crystal layer, a plurality of first transistors, and a first metal layer, forming memory control circuits; a second level overlaying the single crystal layer, and including a plurality of second transistors and a plurality of first memory cells; a third level overlaying the second level, and including a plurality of third transistors and a plurality of second memory cells; where the second transistors are aligned to the first transistors with less than 40 nm alignment error, where the memory cells include a NAND non-volatile memory type, where some of the memory control circuits can control at least one of the memory cells, and where some of the memory control circuits are designed to perform a verify read after a write pulse so to detect if the at least one of the memory cells has been successfully written.