Transistor TRIZ Cases

An auxiliary film suppresses oxygen migration from the semiconductor to electrodes, stabilizing Vg-Id characteristics and maintaining low contact resistance.

Alternating lower and upper charge storing layers resolve patterning precision limits to achieve two times higher integration degree.

Dual gate insulator layers enable reliable programming by forming resistive paths without requiring high voltage that damages device reliability.

Hydrogen extraction from an oxide semiconductor channel lowers off-state current below 1×10⁻¹³ A, stabilizing charge retention in solid-state image sensors.

Segmented gates and sidewall charge traps resolve overerase leakage in high-density NOR flash arrays.

Strained silicon-germanium fins on relaxed silicon-carbon bases reduce off-state leakage while preserving thermal stability.

A thin film transistor array panel uses a buffer layer to protect an oxide semiconductor.

Liquid crystal tuning on a TFT substrate steers beams, reducing manufacturing costs for scanning antennas.

Thermally conductive layers integrate within 3D semiconductor stacks to reduce thermal resistance and enable efficient heat removal from high-power components.

Metal-insulator-metal fin capacitors integrate with finFET fabrication flows to boost capacitance density.

A multiple-gate transistor structure wraps a gate electrode around a semiconductor fin to enhance electrostatic control.

Alternating SiOx and SiCyNz films reduce high-temperature processing needs, enabling flexible substrates while maintaining reliable insulation.

Optimized trench geometry in a vertical field effect transistor reduces on-resistance without deteriorating turn-off tolerance.

Gate electrodes fill space beside strip-shaped semiconductor regions to create a quasi-planar structure, reducing photolithographic step complexity.

Epitaxial refilling of asymmetric cavities creates strain-inducing source-drain regions with overlapping nose portions.

Selective etching of alternating semiconductor layers creates nanowire pillars supported by spacers, enabling replacement metal gate integration.

A half-bridge energy recovery circuit redirects switching energy to storage components.

A power supply control device estimates wire temperature using current detection and adjusted heat dissipation time constants to protect switch elements.

Segmented gate electrodes apply local electric fields to modulate nanochannel conductance, resolving sensitivity and complexity trade-offs.

A load driver adjusts input voltage via a temperature signal to maintain current flow during high-temperature semiconductor conduction.

Calculating PWM duty against a threshold detects load-side abnormalities in vehicle display panels that enable-signal monitoring misses.

Grouping transistors by physical characteristics reduces doping differences, minimizing process deviations that degrade signal detection accuracy.

A gate voltage control semiconductor element connected to a depletion type MOSFET pull-up element manages the gate potential of an insulated-gate device.

Nano air-pores in the phase-change material increase local current density, reducing reset current without shrinking bottom electrode contact areas.

A gallium nitride lateral gate insulated bipolar transistor uses a side plate to control the channel.

Segmenting the metal gate with an air gap lowers parasitic capacitance between the gate and source/drain contacts, improving gate control effectiveness.

Split-gate finFETs use a control gate bias to correct threshold voltage shifts caused by negative bias temperature instability and hot carrier effects.

Insulator spacers position pseudo gates around fins, preventing misalignment that causes irregular source and drain formation.

Removing a sacrificial spacer creates an air gap between the bit line and storage node contact, reducing RC delay without adding processing steps.

A segmented protective film opening exposes the oxide semiconductor channel region to reduce membrane stress and facilitate gas annealing.

Simultaneous patterning of interlayer dielectric layers merges contact hole formation to reduce mask counts while maintaining touch functionality.

Epitaxial growth controls channel layer thickness and impurity concentration distributions across a semiconductor wafer surface.

A diffusion-resistant carbon doped region suppresses impurity migration in active patterns of three-dimensional semiconductor memory devices.

Merging compensation transistor gates with divided gate lines minimizes non-transmittance area, sustaining reliability and resolution above 400 PPI.

Stacked nanowire transistors use varying cross-sectional shapes to optimize strain independently for n-channel and p-channel device sections.

Controls lateral over-etching by adjusting chamber pressure and chuck temperature during dry etching, ensuring consistent critical dimensions.

Gapfill dielectric planarization enables self-aligned contacts that provide low uniform resistance while maintaining process latitude at advanced nodes.

Segmented back-to-back MOSFETs eliminate back-grinding and source-to-source resistance.

An integrated Schottky barrier diode cell directs reverse current away from the drift layer, preventing stacking defect growth and conduction deterioration.

A gate driving circuit uses a class B amplifier structure to generate stable high and low level signals without dead time control.

Integrated gate drivers in bidirectional GaN switches eliminate external power supplies, reducing circuit complexity while maintaining high efficiency.

Arranging contact electrodes over a guard ring isolates the Schottky junction from sputter etching variations, stabilizing reverse leakage current.

A thin film transistor uses a dual-layer insulating laminate to improve interface properties and repair defects in the semiconductor layer.

Gate-all-around transistors with strained Ge channels improve carrier mobility while suppressing short-channel effects at sub-10nm nodes.

A display device driving transistor uses separate gate electrodes and storage capacitors to perform fast sampling operations.

A semi-continuous active region standard cell design merges transistor sources and drains under a common gate to maintain structural continuity.

An amorphous III-V compound layer provides electrical isolation between devices, suppressing interference while enabling silicon integration.

A dummy support pattern compensates for dishing-induced concave recesses in the insulation layer, ensuring uniform deposition and stable electrical connections.

A phase change memory cell uses a low thermal conductivity dielectric spacer on the cap portion sidewall to confine heat within the storage structure.