Amorphous III-V Layer Isolation on Silicon Substrates
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Solution Overview
Problem
III-V compound semiconductor devices have not been effectively integrated with silicon devices, limiting their application due to interference between devices formed on the semiconductor substrate.
Innovation Solution
A semiconductor substrate is created with a first silicon-containing layer, a single crystalline III-V compound semiconductor layer, and an amorphous III-V compound semiconductor layer, where the single crystalline layer is in contact with the amorphous layer and extends between them, with the amorphous layer providing electrical isolation by transforming a portion of the single crystalline layer through an implantation process, allowing for effective integration and isolation of devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If III-V compound semiconductor layers are grown on silicon substrate, then integration of III-V devices with silicon devices is enabled, but interference between devices occurs due to lack of effective isolation
Solution Approach 1:
The semiconductor substrate is divided into multiple regions with different crystal structures: a first region containing a single crystalline III-V compound semiconductor layer for forming first devices, and a second region containing an amorphous III-V compound semiconductor layer for forming second devices. This spatial segmentation enables independent device formation and electrical isolation between the two device types, resolving the interference problem while maintaining integration capability.
Solution Approach 2:
Different regions of the semiconductor substrate are given different local properties: the first region maintains single crystalline structure to support high-performance III-V devices, while the second region is transformed to amorphous structure to provide electrical isolation and support silicon-based devices. This local differentiation allows each region to be optimized for its specific device type without affecting the other.
2Reliability
If a single crystalline III-V compound semiconductor layer is formed on the entire substrate, then high performance devices can be fabricated, but device isolation and interference suppression become difficult
Solution Approach 1:
The crystal structure parameter of the III-V compound semiconductor layer is changed from single crystalline to amorphous in the second region through ion implantation or other transformation processes. This parameter change creates an amorphous layer with high electrical resistance that serves as an effective isolation barrier, while the first region retains its single crystalline structure for optimal device performance.
3Object-affected harmful factors
If amorphous III-V compound semiconductor layer is used for isolation, then device interference is suppressed, but the area for high-performance single crystalline devices is reduced
Solution Approach 1:
The substrate is segmented into distinct first and second regions, with the amorphous layer confined to the second region. This segmentation ensures that the amorphous isolation layer does not encroach on the first region where single crystalline high-performance devices are fabricated, thus maximizing the active device area while still providing effective interference suppression.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the integration of III-V compound semiconductor devices with silicon devices, significantly suppressing interference between them, facilitating the formation of a system on chip (SoC) structure and enhancing device isolation by utilizing the amorphous layer's high resistance.
Implementation Method 1
the amorphous III-V compound semiconductor layer is disposed on the first silicon-containing layer in the second region... significantly suppressing interference between them, facilitating the formation of a system on chip (SoC) structure and enhancing device isolation by utilizing the amorphous layer's high resistance
Implementation Method 2
transforming a portion of the single crystalline layer through an implantation process
Data Source
AI summary
A semiconductor device, a semiconductor substrate and a method of forming the same are disclosed. The semiconductor substrate includes a first silicon-containing layer, a single crystalline III-V compound semiconductor layer and an amorphous III-V compound semiconductor layer. The first silicon-containing layer has a first region and a second region. The single crystalline III-V compound semiconductor layer is disposed on the first silicon-containing layer in the first region. The amorphous III-V compound semiconductor layer is disposed on the first silicon-containing layer in the second region.