Nanosheet Gate Air Gap for Parasitic Capacitance Reduction
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Solution Overview
Problem
As CMOS nano devices scale down, the increased height of the gate leads to higher parasitic capacitance between the gate and source/drain contact, affecting device performance.
Innovation Solution
Creating an air gap in the metal gate between the first and second channel regions reduces the overlap and thus the parasitic capacitance by forming a semiconductor device with a metal gate that spans across multiple nanosheets, including an air gap between the channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate height is increased to achieve enough effective gate width, then the device can maintain sufficient gate control, but the parasitic capacitance between the gate and S/D contact increases
Solution Approach 1:
The gate is segmented into two separate gates with an air gap between them, dividing the continuous gate structure into discrete sections that reduce capacitive coupling with the source/drain contacts
Solution Approach 2:
The air gap is extracted from the gate structure, removing the problematic overlapping region between the gate and S/D contact that causes parasitic capacitance, while retaining the necessary gate width for effective control
Data Source
AI summary
A semiconductor device comprising a first channel region located on a substrate and a second channel region located on the substrate. A metal gate that extends across the first channel to the second channel and an air gap located in the metal gate, wherein the air gap is located between the first channel region and the second channel region, wherein the metal gate is located on top of the air gap.