High-Density NOR Flash Memory Sidewall Charge Storage

The gate structure is segmented into multiple independent gates (first gate and second gate) positioned at different locations relative to the charge trap structure. This segmentation allows selective erasing of specific memory cells by applying voltage to only the relevant gate, preventing the overerase problem where all cells in a block must be erased together. The segmented gate configuration enables precise control over which memory cells are affected by erase operations.

The patent transitions from a planar memory cell arrangement to a three-dimensional configuration by stacking memory cells vertically with charge trap structures positioned between source and drain regions. This vertical stacking in the third dimension increases storage density while maintaining the ability to selectively access and erase individual cells through the segmented gate structure, resolving both the density and overerase issues simultaneously.

The patent implements local quality by positioning charge trap structures specifically in the lower portion of the channel region between source and drain, rather than uniformly throughout. The first gate controls the upper portion and the second gate controls the lower portion where charge traps are located. This localized charge storage approach increases density while preventing leakage currents by confining charges to specific regions with appropriate electrical control.

The charge trap structure serves as an intermediary between the gates and the channel, mediating charge storage and release. By introducing this intermediate layer with specific electrical properties, the patent enables controlled charge accumulation that increases storage density while the dual-gate configuration provides precise control to prevent unwanted leakage currents through the channel.