Aggressively Strained SiGe FET Fin Structure
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Solution Overview
Problem
Current field-effect transistors (FETs) face challenges with high off-state leakage and process temperature constraints when using silicon-germanium (SiGe) channels with high germanium content, while low-Ge content SiGe offers better thermal stability but requires aggressive straining to maintain performance.
Innovation Solution
The fabrication of a field-effect transistor structure involving aggressively strained low-Ge content SiGe channels lattice-matched to a relaxed carbon-doped silicon (Si:C) structure, using shallow trench isolation (STI) with dielectric walled aspect ratio trapping (ART) trenches, and epitaxial growth of SiGe fins on recessed Si:C fins to achieve reduced off-state leakage and improved thermal stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If high germanium content SiGe channels are used, then device performance is improved, but off-state leakage increases and process temperature constraints occur
Solution Approach 1:
The patent applies local quality by creating distinct regions within the channel structure: a relaxed Si:C lower portion and an aggressively strained SiGe upper portion. This allows different sections to have different material compositions and strain states, enabling high performance in the channel while managing leakage through the specific properties of the SiGe region.
Solution Approach 2:
The patent uses composite materials by combining silicon-carbon (Si:C) and silicon-germanium (SiGe) in a vertically stacked fin structure. The relaxed Si:C base provides thermal stability and lattice matching, while the strained SiGe layer enhances carrier mobility, creating a composite structure that balances performance and reliability.
2Reliability
If high germanium content SiGe channels are used, then device performance is improved, but process temperature constraints occur
Solution Approach 1:
The relaxed Si:C lower portion provides a thermally stable base that can withstand higher process temperatures, while the SiGe upper portion is optimized for performance. This local differentiation allows the structure to maintain thermal stability during fabrication while achieving high device performance.
Solution Approach 2:
The composite Si:C/SiGe structure leverages the superior thermal stability of carbon-doped silicon in the lower region, which serves as a robust foundation that tolerates process temperatures, while the upper SiGe region provides the desired electrical performance characteristics.
3Temperature
If low-Ge content SiGe is used, then thermal stability is improved, but aggressive straining is required to maintain performance
Solution Approach 1:
The patent concentrates the aggressive straining in the upper SiGe portion where it is most needed for performance, while the lower Si:C portion remains relaxed and provides thermal stability. This localized approach to strain management reduces overall process complexity compared to uniformly straining the entire channel.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a FET structure that performs similarly to high-Ge content SiGe channels while reducing off-state leakage and preserving thermal stability, making it suitable for high-performance CMOS applications.
Implementation Method 1
epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more dielectric walled ART trenches
Implementation Method 2
aggressively strained low-Ge content SiGe channels lattice-matched to a relaxed carbon-doped silicon (Si:C) structure
Data Source
AI summary
In a method for fabricating a field-effect transistor (FET) structure, forming a shallow trench isolation (STI) structure on a semiconductor substrate, wherein the STI structure includes dielectric structures that form one or more dielectric walled aspect ratio trapping (ART) trenches. The method further includes epitaxially growing a first semiconductor material on the semiconductor substrate and substantially filling at least one of the one or more ART trenches, and recessing the first semiconductor material down into the ART trenches selective to the dielectric structures, such that the upper surface of the first semiconductor material is below the upper surface of the dielectric structures. The method further includes epitaxially growing a second semiconductor material on top of the first semiconductor material and substantially filling the ART trenches to form a semiconductor fin that comprises an upper portion comprising the second semiconductor material and a lower portion comprising the first semiconductor material.