Vertical FET Trench Optimization for On-Resistance and Turn-Off Tolerance
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Solution Overview
Problem
Conventional vertical field effect transistors face a trade-off between reducing on-resistance and improving tolerance at turn-off, making it difficult to achieve both properties simultaneously.
Innovation Solution
A semiconductor device with a face-down mountable chip-size package type structure, featuring a silicon substrate with a low-concentration impurity layer and a vertical field effect transistor design that includes trenches, gate insulating films, and connection portions, where the trench-to-trench distance and connection portion lengths are optimized to reduce on-resistance and enhance tolerance at turn-off.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an orthogonal structure is used to reduce on-resistance, then on-resistance is reduced, but tolerance at turn-off deteriorates
Solution Approach 1:
The patent applies local quality by creating different impurity concentration zones within the semiconductor structure. Specifically, a low-concentration impurity layer is formed on the semiconductor substrate, and connection portions with specific dimensions are created to have different electrical properties than surrounding regions. This allows the structure to simultaneously achieve low on-resistance through optimized conduction paths and high tolerance at turn-off through controlled impurity distribution in different locations.
Solution Approach 2:
The patent utilizes parameter changes by precisely controlling impurity concentrations and geometric dimensions. The low-concentration impurity layer has a specifically controlled doping level, and the connection portions have defined length and width parameters. By adjusting these parameters, the device achieves both reduced on-resistance and improved tolerance at turn-off, resolving the traditional trade-off between these two characteristics.
2Object-generated harmful factors
If a parallel structure is used to improve tolerance at turn-off, then tolerance at turn-off is improved, but on-resistance increases
Solution Approach 1:
The patent applies segmentation by dividing the current conduction path into multiple regions with different functions. The structure includes a low-concentration impurity layer, body regions, source regions, and connection portions, each serving specific purposes. This segmentation allows optimization of each region independently to achieve both low on-resistance and high tolerance at turn-off simultaneously.
Solution Approach 2:
The patent transitions from conventional two-dimensional planar structures to a more complex three-dimensional architecture with vertically stacked layers and laterally extended connection portions. This dimensional change enables independent optimization of vertical current flow (for low on-resistance) and lateral field distribution (for high tolerance at turn-off), breaking the traditional trade-off between these parameters.
Data Source
AI summary
Provided is a first vertical field effect transistor in which first source regions and first connection portions via which a first body region is connected to a first source electrode are disposed alternately and cyclically in a first direction in which first trenches extend. In a second direction orthogonal to the first direction, Lxm≤Lxr≤0.20 μm holds true where Lxm denotes a distance between adjacent first trenches and Lxr denotes the inner width of a first trench. The lengths of the first connection portions are in a convergence region in which the on-resistance of the vertical field effect transistor at the time when a voltage having a specification value is applied to first gate conductors to supply current having a specification value does not decrease noticeably even when the lengths of the first connection portions are made much shorter.