Gate Driving Circuit with Class B Amplifier for Low Power
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Solution Overview
Problem
Conventional gate driving circuits for power supply apparatuses require dead time controlling and an output buffer to stabilize high and low level signals, leading to increased power consumption and manufacturing costs.
Innovation Solution
A gate driving circuit with a class B amplifier structure that eliminates the need for dead time controlling, utilizing a bias unit with N-MOSFET and P-MOSFET transistors and an amplifying unit with series-connected N-MOSFET and P-MOSFET transistors, along with a level shifter and constant current sources, to provide a gate signal without simultaneous switching of the transistors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If dead time controlling and output buffer are used to stabilize high and low level signals, then signal stability is improved, but power consumption increases
Solution Approach 1:
The patent removes the dead time control mechanism and output buffer from the gate driving circuit. By extracting these components, the circuit achieves signal stability through the intrinsic complementary switching action of the first N-MOSFET and first P-MOSFET in the bias unit, eliminating the need for additional power-consuming dead time control and buffering stages.
Solution Approach 2:
The gate driving circuit uses the complementary nature of the first N-MOSFET and first P-MOSFET to automatically generate stable high and low level signals without external dead time control. The bias unit self-regulates the signal levels through the turning on and off of these transistors, and the amplifying unit similarly self-regulates the gate signal output, eliminating the need for power-consuming external control mechanisms.
2Reliability
If dead time controlling and output buffer are used to stabilize high and low level signals, then signal stability is improved, but manufacturing cost increases
Solution Approach 1:
The patent removes the dead time control circuitry and output buffer from the gate driving circuit design. By extracting these additional components, the manufacturing process is simplified, reducing the number of devices that need to be fabricated, assembled, and tested, thereby lowering manufacturing costs while maintaining signal stability through the complementary transistor architecture.
3Use of energy by moving object
If class B amplifier structure is used without dead time controlling, then power consumption is reduced, but signal stability may be compromised
Solution Approach 1:
The patent employs asymmetric complementary transistor pairs where the first N-MOSFET and first P-MOSFET have different characteristics optimized for their respective functions. The second N-MOSFET and second P-MOSFET in the amplifying unit are similarly asymmetrically designed. This asymmetry allows each transistor to operate in its optimal region, ensuring stable signal generation without requiring dead time control, thereby maintaining both low power consumption and signal stability.
Data Source
AI summary
A gate driving circuit may include: a bias unit receiving an input signal having preset high and low signal levels, including a first N-MOSFET turned on in the case in which the input signal has the high level and a first P-MOSFET turned on in the case in which the input signal has the low level, and supplying bias powers by the turning-on of the first N-MOSFET and the first P-MOSFET; and an amplifying unit including a second N-MOSFET turned on by receiving the bias power supplied from the first N-MOSFET in the case in which the input signal has the high level and a second P-MOSFET turned on by receiving the bias power supplied from the first P-MOSFET turned on in the case in which the input signal has the low level and providing a gate signal depending on the turning-on of the second N-MOSFET and the second P-MOSFET.