GaN Lateral Gate IGBT for Parasitic JFET Elimination
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Solution Overview
Problem
Existing insulated gate bipolar transistors (IGBTs) using silicon or silicon carbide substrates suffer from parasitic junction field effect transistor formation, which limits their operation speed and increases conduction resistance due to depletion regions formed by N-type cathodes and P-type regions.
Innovation Solution
The use of a gallium nitride (GaN) substrate with specific GaN layers and an aluminum gallium nitride (AlGaN) barrier layer, forming a lateral structure that includes a gate with a side plate connected to the side wall for channel control, allowing for parallel junction field effect transistor (JFET) and bipolar junction transistor (BJT) configurations, enhancing operation speed and reducing conduction resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a vertical DMOS structure with N-type cathodes and P-type regions is used, then the device can function as an IGBT, but parasitic junction field effect transistors are formed that limit operation speed and increase conduction resistance
Solution Approach 1:
The patent transitions from a vertical DMOS structure to a lateral structure where the gate electrode is positioned laterally adjacent to the channel rather than vertically above it. This dimensional change eliminates the formation of parasitic JFETs at the cathode-region junctions while maintaining IGBT functionality, thereby improving operation speed and reducing conduction resistance.
Solution Approach 2:
The invention extracts and removes the problematic N-type cathode and P-type region configuration that creates parasitic JFETs. By reconfiguring the device architecture to a lateral structure with a gate electrode positioned beside the channel, the parasitic junctions are eliminated while preserving the essential IGBT switching function.
2Reliability
If a vertical DMOS structure with N-type cathodes and P-type regions is used, then the device can function as an IGBT, but conduction resistance increases due to depletion regions
Solution Approach 1:
The lateral structure configuration changes the spatial arrangement of the gate electrode from vertical to lateral positioning, which eliminates the depletion region formation at cathode-region junctions. This dimensional reconfiguration reduces conduction resistance and energy loss while maintaining IGBT functionality.
3Speed
If a lateral gate structure with GaN layers is used, then operation speed improves and conduction resistance reduces, but device structure becomes more complex
Solution Approach 1:
The patent employs composite material structures including multiple GaN layers with different conductive types (n-type, p-type, intrinsic) stacked in a lateral configuration. This composite structure enables high-speed operation and low conduction resistance while managing the inherent complexity through systematic layer integration and functional optimization.
Data Source
AI summary
The present invention discloses an insulated gate bipolar transistor (IGBT) and a manufacturing method thereof. The IGBT includes: a gallium nitride (GaN) substrate, a first GaN layer with a first conductive type, a second GaN layer with a first conductive type, a third GaN layer with a second conductive type or an intrinsic conductive type, and a gate formed on the GaN substrate. The first GaN layer is formed on the GaN substrate and has a side wall vertical to the GaN substrate. The second GaN layer is formed on the GaN substrate and is separated from the first GaN layer by the gate. The third GaN layer is formed on the first GaN layer and is separated from the GaN substrate by the first GaN layer. The gate has a side plate adjacent to the side wall in a lateral direction to control a channel.