FinFET Pseudo Gate Alignment via Insulator Spacers
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Solution Overview
Problem
Existing methods for manufacturing FinFET devices often result in irregularly formed sources and drains due to pseudo gate misalignment or constriction, leading to performance and uniformity issues.
Innovation Solution
A manufacturing method involving a substrate structure with trenches, insulator layers, and pseudo gate structures that wrap around fins, with spacers formed on the insulator layers to create recesses for source and drain formation, preventing undesired connections between fins.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If pseudo gates are formed on fins to define source and drain regions, then device performance is improved, but pseudo gate misalignment causes irregular source and drain formation leading to device reliability degradation
Solution Approach 1:
The patent introduces an intermediary structure (the combination of first and second insulator layers with spacers) between the fin and the pseudo gate structures. This intermediary system provides precise positioning references that ensure accurate alignment of source and drain regions relative to the fin, eliminating the misalignment problems caused by direct pseudo gate formation while maintaining device performance improvements.
Solution Approach 2:
The patent performs preliminary actions by forming the first insulator layer, second insulator layer, and spacers before forming the pseudo gate structures. These preliminary structures establish precise geometric references and positioning frameworks in advance, ensuring that subsequent source and drain formation occurs at the correct locations with proper uniformity, thereby preventing alignment issues before they occur.
2Area of stationary object
If pseudo gates are formed close to fin peripheries to maximize active region, then device area is increased, but source and drain may undesirably connect between adjacent fins reducing device reliability
Solution Approach 1:
The patent uses the second insulator layer and spacers as intermediary structures that physically separate adjacent fin regions. These intermediaries extend between fins and provide isolation barriers that prevent source and drain regions from undesirably connecting between adjacent fins, allowing the active region to be maximized while maintaining reliability through physical separation.
Solution Approach 2:
The patent segments the isolation function by using multiple separate structures (first insulator layer in trenches, second insulator layer covering fins, and spacers at fin corners) rather than a single continuous isolation structure. This segmentation allows precise control over where isolation occurs, enabling source and drain regions to be maximized within each fin while maintaining reliable separation between adjacent fins.
3Reliability
If insulator material is deposited to completely fill trenches for isolation, then isolation effectiveness is improved, but fin structure flexibility and subsequent processing accessibility are reduced
Solution Approach 1:
The patent applies local quality by using the first insulator layer selectively only in the trenches between fins rather than uniformly filling all spaces. This localized application provides effective isolation where needed (between fins) while leaving the fin structures and surrounding areas accessible for subsequent processing steps, optimizing both isolation effectiveness and manufacturing ease.
Data Source
AI summary
The present disclosure provides a semiconductor device and a manufacturing method therefor. The device may include: a semiconductor substrate; a fin projecting from the semiconductor substrate, where trenches are formed on sides of the fin; a first insulator layer partially filling the trenches, where the fin protrudes from the first insulator layer; a second insulator layer covering the fin; a plurality of pseudo gate structures on the second insulator layer, where each pseudo gate structure wraps a part of the fin, where each pseudo gate structure includes a pseudo gate located on the second insulator layer, the plurality of pseudo gate structures includes at least a first pseudo gate structure and a second pseudo gate structure that are spaced from each other, the second pseudo gate structure is located at an edge corner of the fin, and a part of the second pseudo gate structure is on the first insulator layer; spacers, on the first insulator layer and the second insulator layer, at two sides of each of the plurality of pseudo gate structures; and a source or a drain located among the plurality of pseudo gate structures. The present invention can improve reliability of the device.