GAA FET Channel Strain and Gate Control for Sub-10nm Nodes
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Solution Overview
Problem
As semiconductor technology advances to nanometer nodes, Gate-All-Around Field Effect Transistors (GAA FETs) face challenges in achieving optimal performance due to short-channel effects and inadequate control over channel regions, particularly in Fin FETs where the bottom side of the channel is not under close gate control, and in GAA FETs where further improvements are needed for scaled-down dimensions.
Innovation Solution
The implementation of tensile strained Ge nFETs and compressive strained Ge pFETs in GAA FETs is achieved by using strain materials on source/drain regions and introducing stress from substrates, with channel regions made of Ge or SiGe, and source/drain epitaxial layers of GeSn or SiGeSn to introduce stress, allowing for improved electrostatics and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If transistor dimensions are scaled down to sub 10-15 nm technology nodes, then device density and performance are improved, but short-channel effects worsen and gate control over channel region deteriorates
Solution Approach 1:
The patent transitions from planar Fin FET gate control to three-dimensional Gate-All-Around FET structure, where the gate electrode completely surrounds the channel region in all directions including the bottom surface. This dimensional change enables full depletion of the channel region and eliminates short-channel effects that plague scaled-down transistors, achieving both high device density and reliable gate control at sub-10-15 nm nodes
Solution Approach 2:
The patent employs composite material structures including Ge/SiGe channel regions with specific lattice mismatch ratios, high-k gate dielectric layers, and metal gate electrodes. These composite materials enable simultaneous achievement of high carrier mobility, full channel depletion, and stable gate control, resolving the contradiction between scaling for density and maintaining reliability
2Reliability
If Ge channel regions are used to improve carrier mobility, then driving current is enhanced, but lattice mismatch with Si substrate causes misfit dislocations
Solution Approach 1:
The patent segments the channel structure into multiple thin Ge/SiGe layers with controlled thickness ratios. By keeping each Ge layer thinner than the critical thickness for misfit dislocation formation, the structure maintains high Ge content for carrier mobility while preventing crystal structure degradation through careful segmentation of the channel region
Solution Approach 2:
The patent optimizes the lattice mismatch ratio between Ge and SiGe layers, controlling the thickness and composition parameters to remain within ranges that prevent misfit dislocation formation. This parameter optimization enables high Ge content channel regions that maintain both superior carrier mobility and crystal structure stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the driving current and reduces short-channel effects by ensuring fuller depletion in the channel region, leading to better sub-threshold current swing and drain-induced barrier lowering, thus improving the performance of GAA FETs at sub-10-15 nm technology nodes.
Implementation Method 1
tensile strained Ge nFETs and compressive strained Ge pFETs... by using strain materials on source/drain regions and introducing stress from substrates
Data Source
AI summary
A semiconductor device includes a gate-all-around field effect transistor (GAA FET). The GAA FET includes channel regions made of a first semiconductor material disposed over a bottom fin layer made of a second semiconductor material, and a source/drain region made of a third semiconductor material. The first semiconductor material is Si1-xGex, where 0.9≤x≤1.0, and the second semiconductor material is Si1-yGey, where y<x and 0.3≤y≤0.7.