Nanowire Transistor Gate Integration via Selective Etching
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current FINFET fabrication techniques face challenges in integrating replacement metal gate (RMG) processes due to gate patterning issues, particularly when scaling down to nanowire dimensions, which limits the development of smaller device dimensions and enhanced electrostatic control.
Innovation Solution
A method involving the formation of alternating semiconductor layers, selective etching to create nanowires, and the integration of a replacement metal gate (RMG) by using spacers and oxide layers to pattern and support the nanowires, allowing for enhanced gate integration and electrostatic control in FINFET devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If traditional gate patterning techniques are used in FINFET fabrication, then existing manufacturing processes can be maintained, but integration of replacement metal gate (RMG) processes is limited and device dimensions cannot be scaled down effectively
Solution Approach 1:
The fabrication process is divided into distinct stages: forming nanowire structures through selective etching of alternating semiconductor layers, creating spacers for positioning, and separately integrating the metal gate structure. This segmentation allows RMG processes to be integrated without disrupting the entire fabrication flow, enabling scaling to smaller dimensions while maintaining manufacturing feasibility.
2Adaptability or versatility
If alternating semiconductor layers are formed and selectively etched to create nanowires, then RMG integration is enabled, but fabrication process complexity increases
Solution Approach 1:
Alternating layers of first and second semiconductor materials are formed in advance before the metal gate integration step. The selective etching of these layers to create nanowire structures with spacers is completed beforehand, establishing a prepared substrate that readily accepts the metal gate structure. This preliminary preparation simplifies the overall integration process despite the added initial complexity.
Solution Approach 2:
The spacers formed from the selectively etched alternating layers serve as intermediary structures that facilitate the integration of the metal gate. These spacers provide mechanical support and positional guidance for the gate structure, enabling seamless integration of RMG processes while managing the complexity of the fabrication sequence.
3Reliability
If nanowire structures with vertical dimension less than 10 nanometers are created, then electrostatic control is enhanced, but manufacturing precision requirements increase
Solution Approach 1:
The vertical dimension of the nanowire structures is controlled by adjusting the thickness parameters of the alternating semiconductor layers during formation. By precisely controlling the layer thicknesses to produce nanowires with vertical dimensions less than 10 nanometers, the patent achieves enhanced electrostatic control while managing manufacturing precision through parameter optimization rather than process complexity increases.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enables the integration of RMG processes in nanowire transistors, facilitating the evolution of smaller FINFET devices with improved electrostatic control and compatibility with traditional FINFET processing techniques.
Implementation Method 1
selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers
Data Source
AI summary
A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.