Semi-Continuous Active Region Standard Cell Design
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Solution Overview
Problem
The use of shallow trench isolation (STI) in standard cells can degrade the drive capability of transistors, especially when silicon germanium or silicon carbide is formed in the source/drain regions, leading to performance issues due to the proximity of the gate to STI regions.
Innovation Solution
Implementing a semi-continuous active region standard cell design where transistors with discontinuous active regions are made continuous under specific configurations, such as connecting drains/sources to the gate or to a source voltage, to reduce the impact of STI regions and enhance transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If shallow trench isolation (STI) is used to separate transistors, then device isolation and manufacturing feasibility are improved, but transistor drive capability and performance are degraded
Solution Approach 1:
The patent extracts and removes the STI structure from between adjacent transistors that share a common gate. By eliminating the isolating trench in this specific configuration, the harmful effect on transistor drive capability is removed while maintaining the necessary isolation through alternative means (common gate structure and other STI regions), thus resolving the contradiction between ease of manufacture and transistor performance.
Solution Approach 2:
The patent merges the active regions of adjacent transistors into a continuous active region when they share a common gate. This merging eliminates the need for STI isolation between these specific transistors, allowing the active regions to be continuous and improving drive capability while maintaining device isolation through the common gate structure and other STI regions.
2Speed
If silicon germanium or silicon carbide is formed in source/drain regions to improve mobility, then carrier mobility is enhanced, but transistor speed is reduced when gate is close to STI region
Solution Approach 1:
The patent removes the STI structure that is causing the performance degradation. By extracting the isolating trench from between transistors with common gates, the harmful proximity effect is eliminated, allowing the silicon germanium or silicon carbide enhanced mobility to fully benefit transistor speed without the counteracting STI proximity penalty.
Solution Approach 2:
The patent combines the source/drain regions into a continuous structure under the common gate, eliminating the STI-induced performance degradation. This merging allows the high-mobility silicon germanium or silicon carbide material to operate at full effectiveness, resolving the speed reduction issue while maintaining the mobility enhancement.
3Reliability
If transistors are separated by STI regions, then device isolation is achieved, but active region continuity is broken causing performance loss
Solution Approach 1:
The patent merges adjacent active regions into a continuous active region when transistors share a common gate. This merging maintains the stability and continuity of the active region composition, eliminating performance loss while device isolation is maintained through the common gate structure and other STI regions.
Solution Approach 2:
The patent extracts and removes the STI structure from between transistors with common gates. By taking out this isolating element, active region continuity is restored and maintained, eliminating performance degradation while necessary device isolation is achieved through alternative means.
Data Source
AI summary
A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.