Quasi-Planar Gate Electrodes for Compact FinFET Devices
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Solution Overview
Problem
Existing FinFET devices face challenges in miniaturization, particularly when multiple parallel strip-shaped semiconductor regions are involved, due to the limitations of gate electrode placement and the complexity of achieving a flat structure, which affects current-carrying capacity and manufacturing efficiency.
Innovation Solution
The gate electrodes are designed to completely fill the space on either side of the strip-shaped semiconductor region, allowing for a quasi-planar structure that facilitates smaller device dimensions and easier electrical connections, achieved through a substrate transfer technique and CMP process without additional steps, enabling symmetrical channel regions and high component density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Length of moving object
If the device uses conventional gate electrode placement with connection regions on either side of the strip-shaped semiconductor region, then the device structure is established, but the device size cannot be sufficiently reduced and photolithographic steps become critical due to non-flat structure
Solution Approach 1:
The gate electrodes are extended into the third dimension by making them fill the space on either side of the strip-shaped semiconductor region over the width of the connection regions. This vertical extension creates a quasi-planar structure that eliminates height differences, allowing photolithographic steps to be performed without critical alignment issues while reducing the overall device footprint.
Solution Approach 2:
The gate electrodes are formed to completely fill the space beside the strip-shaped semiconductor region before the connection regions are finalized. This preliminary formation of the gate electrode structure creates a flat surface that simplifies subsequent photolithographic processing and connection region formation.
2Power
If multiple parallel strip-shaped semiconductor regions are used to increase current-carrying capacity, then higher current capacity is achieved, but device size and complexity increase
Solution Approach 1:
Multiple strip-shaped semiconductor regions are arranged in parallel and connected to common source and drain regions. The gate electrodes are formed on both sides of each strip, creating a merged structure where multiple transistors share common elements. This increases current-carrying capacity while maintaining a compact footprint through the quasi-planar configuration.
Solution Approach 2:
The invention utilizes vertical space by extending gate electrodes to fill the space on either side of the strip-shaped semiconductor region. This three-dimensional configuration allows multiple parallel strips to be packed more densely, increasing current capacity per unit area without proportionally increasing the overall device area.
3Length of moving object
If the gate electrodes do not completely fill the space beside the strip-shaped semiconductor region, then manufacturing is simpler, but the device cannot achieve very small dimensions and connection regions require more space
Solution Approach 1:
The gate electrodes are designed to completely fill the space on either side of the strip-shaped semiconductor region over the width of the connection regions. This full-space filling approach in the vertical dimension creates a quasi-planar structure that eliminates height differences, enabling miniaturization while simplifying the positioning of connection regions.
Data Source
AI summary
The invention relates to a semiconductor device (10) consisting of a substrate (11) and a semiconductor body (2) comprising a strip-shaped semiconductor region (3,3A,3B) of silicon in which a field effect transistor is formed, wherein a source region (4) of a first conductivity type, a channel region (33) of a second conductivity type opposed to the first, and a drain region (5) of the first conductivity type are arranged in succession, successively, seen in the longitudinal direction of the strip-shaped semiconductor region (3,3A,3B), and wherein the channel region (33) is provided with a gate dielectric (6), on which a first gate electrode (7) is present on a first vertical side of the strip-shaped semiconductor region (3,3A,3B), which gate electrode (7) is provided with a first connection region (7A), and on which a second gate electrode (8) is present on a second vertical side of the strip-shaped semiconductor region (3,3A,3B) positioned opposite the first vertical side, which second gate electrode (8) is provided with a second connection region (8A). According to the invention the first and second gate electrodes (7,8) completely fill the space on either side of the strip-shaped semiconductor region (3,3A,3B) over the width of the connection regions (7A,8A). In a preferred embodiment the gate electrodes (7,8) each border a horizontal side of the strip-shaped semiconductor region (3,3A,3B). The device (10) according to the invention is very compact, suitable for the sub 45 nm domain and easy to manufacture.