Self-Aligned Active Trench Contact for MOS Transistors
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Solution Overview
Problem
In advanced technology nodes, such as the 45 nanometer node and beyond, forming contacts to source/drain regions of MOS transistors with uniform low resistance electrical connections is challenging, and existing processes lack sufficient process latitude to maintain cost-effective fabrication of integrated circuits.
Innovation Solution
The implementation of self-aligned contacts is achieved by forming a gapfill dielectric layer that fills spaces between MOS gates, planarizing it to the tops of gate structures, forming a contact pattern that exposes areas for multiple self-aligned contacts, removing the gapfill dielectric layer, and depositing a contact metal layer that abuts the sidewalls, which is then planarized to the tops of the gate structures.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional contact formation processes are used at 45 nanometer node and beyond, then fabrication cost is controlled, but uniform low resistance electrical connections cannot be achieved
Solution Approach 1:
A gapfill dielectric layer is formed and planarized before contact hole etching to create a flat surface. This preliminary planarization action ensures uniform contact etch depth and consistent electrical properties across all contacts, resolving the contradiction by enabling reliable electrical connections while maintaining a controlled fabrication process through staged preparation steps.
Solution Approach 2:
The gapfill dielectric layer acts as an intermediary material between the gate structures and the contact holes. It provides mechanical support and defines the contact formation area, allowing precise control of contact geometry and resistance while simplifying the overall fabrication process through its protective and structural functions.
2Ease of manufacture
If process latitude is increased to maintain cost-effective fabrication, then manufacturing flexibility improves, but contact uniformity and resistance control deteriorate
Solution Approach 1:
The process utilizes parameter changes in the gapfill dielectric layer formation and planarization steps to achieve contact uniformity. By controlling dielectric layer thickness, planarization depth, and etch parameters, the method maintains precise contact geometry and resistance control while allowing flexibility in fabrication conditions and process variations.
3Manufacturing precision
If self-aligned contact method is implemented, then contact resistance uniformity improves, but process sequence complexity increases
Solution Approach 1:
The method merges the gapfill dielectric formation, contact hole definition, and contact etch steps into a self-aligned process sequence. The gapfill layer serves multiple functions: defining contact areas, protecting gate structures during etching, and providing a planar surface. This merging of functions into a single integrated process achieves uniform contact resistance while managing complexity through functional consolidation.
Data Source
AI summary
An integrated circuit and method includes self-aligned contacts. A gapfill dielectric layer fills spaces between sidewalls of adjacent MOS gates. The gapfill dielectric layer is planarized down to tops of gate structures. A contact pattern is formed that exposes an area for multiple self-aligned contacts. The area overlaps adjacent instances of the gate structures. The gapfill dielectric layer is removed from the area. A contact metal layer is formed in the areas where the gapfill dielectric material has been removed. The contact metal abuts the sidewalls along the height of the sidewalls. The contact metal is planarized down to the tops of the gate structures, forming the self-aligned contacts.