Semiconductor Channel Layer Thickness and Impurity Distribution Control
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Solution Overview
Problem
Existing semiconductor devices, such as SiC-MISFETs, face challenges in reducing variations in device characteristics like gate threshold voltage and ON-resistance across a semiconductor wafer surface, particularly due to variations in channel layer thickness and impurity concentration, which become more pronounced as wafer diameter increases.
Innovation Solution
The method involves controlling the epitaxial growth of a channel layer with a specific impurity concentration and thickness distribution, and correlating these distributions with the gate insulation film thickness to compensate for variations, thereby reducing the overall variation in device characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the wafer diameter is increased to improve productivity, then the number of devices per wafer increases, but the variations in device characteristics (gate threshold voltage and ON-resistance) across the wafer surface increase
Solution Approach 1:
The patent applies local quality by creating specific spatial distributions of impurity concentration and thickness in the channel layer. The impurity concentration is deliberately made higher in the central region and lower in the peripheral region, while the thickness is made lower in the central region and higher in the peripheral region. These localized variations compensate for the natural variations that occur across the wafer surface during epitaxial growth, thereby reducing device characteristic variations even on large-diameter wafers.
Solution Approach 2:
The patent employs parameter changes by systematically varying the impurity concentration and thickness parameters of the channel layer across different regions of the wafer. By controlling the epitaxial growth conditions to achieve specific impurity concentration distributions (higher in center, lower at periphery) and thickness distributions (lower in center, higher at periphery), the patent compensates for process-induced variations and maintains consistent device characteristics across the entire wafer surface.
2Reliability
If the impurity concentration in the channel layer is increased to reduce ON-resistance, then the channel resistance decreases, but the variations in device characteristics across the wafer surface increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform impurity concentration distribution in the channel layer, with higher concentrations in the central region and lower concentrations in the peripheral region. This localized variation compensates for the fact that epitaxial growth conditions naturally vary across the wafer surface, ensuring that the effective impurity concentration (and thus ON-resistance) remains consistent across all devices on the wafer, even though the absolute concentration values differ by location.
3Reliability
If the thickness of the channel layer is reduced to improve device performance, then the ON-resistance decreases, but the variations in gate threshold voltage across the wafer surface increase
Solution Approach 1:
The patent applies local quality by creating a non-uniform thickness distribution in the channel layer, with thinner regions in the center and thicker regions at the periphery. This compensates for the natural thickness variations that occur during epitaxial growth across the wafer surface. By making the channel layer thinner in the center where growth tends to be more uniform, and thicker at the periphery where growth variations are larger, the patent achieves consistent gate threshold voltage across all devices.
4Manufacturing precision
If the epitaxial growth conditions are controlled to reduce variations in channel layer thickness, then the manufacturing precision improves, but the productivity decreases due to longer process time or more restrictive conditions
Solution Approach 1:
The patent employs parameter changes by intentionally creating controlled non-uniform thickness and impurity concentration distributions rather than attempting to achieve perfect uniformity. This approach allows the use of more relaxed epitaxial growth conditions that are faster and more productive, while still achieving the desired compensation effect. The key is to control the gradient of variations rather than eliminate variations entirely, which maintains productivity while achieving the necessary precision.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces variations in gate threshold voltage and ON-resistance across the semiconductor wafer surface, improving yield rates and device consistency, even on larger wafers.
Implementation Method 1
a channel layer which is in contact with at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer is formed
Data Source
AI summary
A method of producing a semiconductor device including steps (A) and (B). Step (A) is preparing a semiconductor epitaxial wafer including a plurality of device regions, each including a body region contacting a semiconductor layer. Step (B) is forming a channel layer contacting at least a part of the body region by epitaxial growth of a semiconductor on a surface of the semiconductor layer. The channel layer contains an impurity at a concentration ranging from 1×1018 cm−3 to 1×1019 cm−3, inclusive, and has a thickness ranging from 10 nm to 100 nm, inclusive. In the step (B), a condition for the epitaxial growth is controlled so that, in a plane parallel to the main surface of the semiconductor wafer, a thickness distribution in the channel layer and a concentration distribution of the impurity in the channel layer are negatively correlated to each other.