Air Gap Between Bit Line and Storage Node Contact
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Solution Overview
Problem
As memory cell sizes decrease, the RC delay between the bit line and storage node contact increases, affecting the operation of dynamic random access memory (DRAM) devices, as conventional manufacturing methods fail to effectively reduce this delay.
Innovation Solution
A semiconductor device and manufacturing method that form an air gap between the bit line and storage node contact by removing a sacrificial spacer, reducing RC delay without damaging the peripheral circuit, and forming the air gap without adding extra processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the memory cell size is reduced to increase storage capacity, then the storage density is improved, but the RC delay between the bit line and storage node contact increases
Solution Approach 1:
The patent extracts the problematic conductive material (sacrificial spacer) from the region between the bit line and storage node contact, replacing it with an air gap. This removal of conductive material eliminates the parasitic capacitance and resistance that cause RC delay, while preserving the electrical connection between the bit line and storage node contact through the air gap region.
Solution Approach 2:
The patent applies different properties to different regions: the air gap is created specifically in the region between the bit line and storage node contact to reduce RC delay, while the rest of the structure maintains its original conductive properties for proper electrical function. This localized modification optimizes performance without compromising overall device functionality.
2Speed
If an air gap is formed between the bit line and storage node contact to reduce RC delay, then the operational speed is improved, but the manufacturing process complexity increases
Solution Approach 1:
The sacrificial spacer is formed during the preliminary stages of the manufacturing process, before the bit line and storage node contact are fully assembled. This preliminary placement of the sacrificial spacer establishes the future air gap region without requiring additional processing steps later, as the air gap is created simply by removing the sacrificial spacer after the main structure is formed.
Solution Approach 2:
The sacrificial spacer serves as a temporary intermediary structure that defines the air gap region during manufacturing. It is formed, used as a template, and then removed to create the final air gap structure. This intermediary approach simplifies the overall process by using a temporary structure rather than requiring direct formation of the air gap through complex etching or deposition processes.
3Area of stationary object
If the spacing between the bit line and storage node contact is reduced to save area, then the area efficiency is improved, but the RC delay increases
Solution Approach 1:
The patent removes the conductive material (sacrificial spacer) from the spacing region between the bit line and storage node contact, replacing it with an air gap. This extraction eliminates the parasitic RC effects that would otherwise be present in the reduced spacing region, allowing tight packing without the penalty of increased RC delay.
Solution Approach 2:
The air gap is created specifically in the critical region between the bit line and storage node contact, applying different electrical properties (air instead of conductive material) to this local area. This allows the spacing to be minimized for area efficiency while the air gap properties prevent RC delay, as the air region does not contribute to parasitic capacitance or resistance.
Data Source
AI summary
The present invention provides a semiconductor device including a semiconductor substrate with a memory cell region and a peripheral region, a gate line in the peripheral region, an etch-stop layer covering the gate line and the semiconductor substrate, a first insulating layer covering the etch-stop layer, two contact plugs disposed on the semiconductor substrate in the peripheral region, two pads disposed on the contact plugs respectively, and a second insulating layer disposed between the pads. The contact plugs are located at two sides of the gate line respectively, and the contact plugs penetrate through the etch-stop layer and the first insulating layer to contact the semiconductor substrate. The second insulating layer is not in contact with the etch-stop layer.