Multiple-Gate Transistor Structure for Sub-50nm Scaling
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Solution Overview
Problem
Conventional bulk silicon MOSFETs face challenges in scaling beyond 50 nm due to difficulties in controlling short-channel effects, which lead to degraded mobility, increased junction leakage, and reliability concerns with aggressive gate dielectric thickness reduction.
Innovation Solution
A multiple-gate semiconductor structure with a gate electrode wrapping around a semiconductor fin on its top and sidewall surfaces, eliminating the need for an etchant mask and incorporating a high permittivity gate dielectric layer and conductive straps for improved manufacturability and performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If heavy channel doping is used to suppress short-channel effects, then short-channel effects are suppressed, but mobility is degraded and junction leakage is enhanced
Solution Approach 1:
The patent transitions from conventional planar single-gate structure to a three-dimensional wrap-around gate structure where the gate electrode wraps around the channel region from top and sidewalls. This dimensional change provides superior electrostatic control over the channel, effectively suppressing short-channel effects without requiring heavy channel doping, thereby preserving carrier mobility while maintaining reliability.
Solution Approach 2:
The gate electrode is segmented into multiple regions (first gate electrode portion on top surface, second gate electrode portions on sidewalls) that independently control different aspects of the channel. This segmentation allows optimized doping profiles in each region to address specific performance requirements without compromising overall device operation.
2Power
If gate dielectric thickness is aggressively reduced to improve drive current, then drive current is improved, but direct tunneling gate leakage current increases and standby power consumption increases
Solution Approach 1:
The patent employs a composite gate dielectric structure comprising multiple layers with different materials and properties. This composite structure provides optimized electrical characteristics that enable effective control of drive current while minimizing direct tunneling leakage, resolving the trade-off between drive current and standby power consumption.
Solution Approach 2:
Different regions of the gate dielectric are assigned different thicknesses and material compositions tailored to local requirements. The wrap-around gate configuration allows the dielectric to be optimized at the channel interface for high drive current while maintaining appropriate thickness in other regions to minimize leakage and standby power consumption.
3Ease of manufacture
If conventional bulk silicon MOSFET structure is used for scaling, then manufacturing is simpler, but control of short-channel effects becomes increasingly difficult
Solution Approach 1:
The patent adopts a three-dimensional wrap-around gate structure where the gate electrode extends over the top surface and wraps around the sidewalls of the channel region. This dimensional evolution from planar to立体 structure provides superior electrostatic control and scaling behavior while remaining compatible with existing semiconductor manufacturing processes.
Solution Approach 2:
The wrap-around gate structure serves multiple functions simultaneously: it provides enhanced electrostatic control for short-channel effect suppression, enables continued scaling into sub-50 nm regime, and maintains compatibility with standard fabrication processes. This multi-functionality resolves the contradiction between manufacturing simplicity and scaling performance.
Data Source
AI summary
A multiple-gate transistor structure which includes a substrate, source and drain islands formed in a portion of the substrate, a fin formed of a semi-conducting material that has a top surface and two sidewall surfaces, a gate dielectric layer overlying the fin, and a gate electrode wrapping around the fin on the top surface and the two sidewall surfaces separating source and drain islands. In an alternate embodiment, a substrate that has a depression of an undercut or a notch in a top surface of the substrate is utilized.