SiC MOSFET Integrated Schottky Barrier Diode Cell
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Solution Overview
Problem
Silicon carbide (SiC) MOSFETs experience conduction deterioration due to stacking defects in the drift layer, leading to increased on-state resistance and reliability issues, which existing methods like improving crystallinity or using external Schottky barrier diodes do not sufficiently address.
Innovation Solution
Incorporating a Schottky barrier diode (SBD) cell integrated within the same chip as the SiC-MOSFET, allowing reverse current to flow through the SBD, thereby suppressing the growth of stacking defects and reducing conduction deterioration, while maintaining a compact chip area and low manufacturing cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If holes are injected to the drift layer from the source electrode side in the reverse conduction state, then the built-in diode conducts current, but stacking defects grow due to recoupling energy of holes and electrons, causing conduction deterioration
Solution Approach 1:
The patent divides the single chip into two functional cells: a MOSFET cell and a Schottky barrier diode cell. The Schottky barrier diode cell is specifically designed to handle reverse conduction current, separating this function from the MOSFET cell. This segmentation prevents holes from being injected into the drift layer of the MOSFET cell during reverse conduction, thereby preventing stacking defect growth and conduction deterioration while maintaining low on-state resistance.
2Reliability
If the Schottky barrier diode cell is integrated on the same chip, then reverse current flows through SBD suppressing stacking defect growth, but chip area and manufacturing complexity increase
Solution Approach 1:
The patent merges the MOSFET cell and Schottky barrier diode cell onto a single chip, creating an integrated power device. The Schottky barrier diode cell is formed adjacent to the MOSFET cell, sharing common structures such as the drift layer and electrodes. This merging allows reverse current to flow through the SBD cell, suppressing stacking defect growth in the drift layer, while maintaining a compact integrated structure rather than separate discrete components.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The integrated SBD cell effectively suppresses conduction deterioration, improving the reliability of the SiC-MOSFET by preventing hole injection into the drift layer, reducing on-state resistance, and maintaining a low heat generation density, even at high temperatures and surge currents.
Implementation Method 1
Incorporating a Schottky barrier diode (SBD) cell integrated within the same chip as the SiC-MOSFET, allowing reverse current to flow through the SBD
Implementation Method 2
The built-in diode of the MOSFET is a pn-junction diode. In the reverse conduction state, the drain electrode is negatively biased with respect to the source electrode, and a current flows from the source electrode toward the drain electrode
Implementation Method 3
In the reverse conduction state, holes are injected to a drift layer from a source electrode side, and electrons are injected to the drift layer from a drain electrode side. A stacking defect from an electric potential in the drift layer may grow due to recoupling energy of the holes and the electrons which are injected to the drift layer
Data Source
AI summary
A semiconductor device including a first electrode, a second electrode, and a silicon carbide layer of which at least a portion is provided between the first electrode and the second electrode, the silicon carbide layer including an n-type first silicon carbide region, a plurality of p-type second silicon carbide regions, and a plurality of n-type third silicon carbide regions. The semiconductor device further includes a plurality of first conductive layers each of which is in contact with the n-type first silicon carbide region, a number n, n being 2, 3, 4 or 5, of first gate electrodes that are provided between two adjacent first conductive layers of the plurality of first conductive layers, and extend in the first direction, and a plurality of first gate insulating layers each of which is provided between one of the n first gate electrodes and the n-type first silicon carbide region.