MIM Fin Capacitor Integration with FinFETs
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Solution Overview
Problem
Conventional fin MOS capacitors exhibit poor performance due to high resistance of narrow semiconductor fins, and planar MIM capacitors have low capacitance per area, limiting the viability of finFET technology for diverse voltage and threshold voltage requirements in integrated circuits.
Innovation Solution
The method involves forming finFETs with different threshold voltages and metal-insulator-metal (MIM) fin capacitors on the same chip, using a process that integrates MIM fin capacitors with the finFET fabrication flow, resulting in enhanced capacitance per area and lower resistance compared to conventional planar MIM capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional fin MOS capacitors are used to achieve higher capacitance per area, then capacitance density is improved, but resistance increases due to narrow semiconductor fins
Solution Approach 1:
The patent changes the material parameter of the capacitor electrodes from semiconductor to metal, which fundamentally alters the resistance characteristic while maintaining the fin structure's capacitance density advantage. This material substitution resolves the contradiction by decoupling the capacitance mechanism (dependent on fin geometry) from the resistance mechanism (dependent on electrode material).
Solution Approach 2:
The invention creates a composite structure combining metal electrodes with the semiconductor fin, forming a metal-insulator-metal (MIM) fin capacitor. This composite approach leverages the high capacitance density of the fin structure while using metal materials to provide low resistance, thereby resolving the technical contradiction between capacitance per area and resistance.
2Reliability
If planar MIM capacitors are used to achieve low resistance, then resistance is reduced, but capacitance per area decreases
Solution Approach 1:
The patent transitions from planar (2D) capacitor geometry to a vertical fin structure (3D), increasing the effective capacitance area without increasing the planar footprint. This dimensional change allows the capacitor to achieve high capacitance per area while maintaining the low resistance benefits of the MIM structure.
Solution Approach 2:
The invention changes the geometric parameter from planar surface area to vertical fin surface area, fundamentally altering how capacitance is achieved. This parameter change enables high capacitance density while maintaining the low resistance characteristics of metal electrodes, resolving the contradiction with planar MIM capacitors.
3Adaptability or versatility
If multiple devices with different threshold voltages are fabricated on the same chip, then design versatility is improved, but process complexity increases
Solution Approach 1:
The patent segments the gate electrode into multiple distinct layers (first conductor layer, second conductor layer) that can be independently patterned and controlled. This segmentation allows different regions of the fin to have different threshold voltages while using a unified fabrication process, thereby improving design versatility without significantly increasing process complexity.
Solution Approach 2:
The multi-layer gate structure serves multiple functions: it enables different threshold voltages for different devices, provides capacitance storage function, and maintains compatibility with standard finFET fabrication processes. This multi-functionality resolves the contradiction by achieving design versatility through a universal process platform.
Data Source
AI summary
An integrated circuit having finFETs and a metal-insulator-metal (MIM) fin capacitor and methods of manufacture are disclosed. A method includes forming a first finFET comprising a first dielectric and a first conductor; forming a second finFET comprising a second dielectric and a second conductor; and forming a fin capacitor comprising the first conductor, the second dielectric, and the second conductor.