OTP Cell Programming Reliability via Dual Gate Insulator
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Solution Overview
Problem
Existing one-time programmable (OTP) memory cells face challenges in achieving reliable programming due to the difficulty in breaking down the gate insulating film with low program voltage, leading to inconsistent resistive path formation and reduced programming success rates.
Innovation Solution
The design incorporates a low voltage (LV) and middle voltage (MV) transistor structure in the OTP cell, where the LV transistor has a thinner gate insulating film to facilitate breakdown at a lower voltage, and additional doped regions are grounded to form additional resistive paths, enhancing programming reliability even if hard breakdown does not occur.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick gate insulating film is used to maintain device reliability, then breakdown voltage increases and programming becomes difficult, but if a thin gate insulating film is used to facilitate breakdown, then device reliability decreases and leakage increases
Solution Approach 1:
The gate insulating film is divided into two distinct layers: a first gate insulating film (thinner, lower breakdown voltage) and a second gate insulating film (thicker, higher breakdown voltage). This segmentation allows the thinner first layer to facilitate programming breakdown while the thicker second layer maintains device reliability and prevents leakage, resolving the contradiction between programming ease and device reliability.
2Productivity
If high program voltage is applied to break down the gate insulating film, then programming speed increases, but device reliability decreases due to potential damage to other structures
Solution Approach 1:
The gate insulating film structure is designed with non-uniform thickness characteristics through the two-layer configuration, where the first gate insulating film has lower breakdown voltage characteristics specifically at the region needed for programming. This allows breakdown to occur at lower voltages (improving device reliability) while still achieving programming functionality, and the structured breakdown path ensures controlled failure mode that maintains overall device integrity.
3Reliability
If the gate insulating film breakdown area is small, then programming voltage can be lower, but the resistive path formed has high resistance and programming is unreliable
Solution Approach 1:
The first gate insulating film is designed to break down first at a lower voltage, creating an initial conductive path. This preliminary breakdown action prepares the structure for subsequent formation of a more robust resistive path involving both gate insulating films, ensuring reliable programming without requiring excessively high voltages that could damage the device.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for reliable programming by forming multiple resistive paths, increasing the success rate and stability of the OTP cell, even when breakdown occurs at the source, drain, or gate insulating film, thereby improving overall programming reliability.
Implementation Method 1
a high dielectric field is applied to a dielectric material such as oxide to allow a tunneling current to flow through the dielectric material. The tunneling current flowing through the dielectric material causes a phenomenon called 'dielectric breakdown.'
Implementation Method 2
a high dielectric field is applied to a dielectric material such as oxide to allow a tunneling current to flow through the dielectric material
Data Source
AI summary
A non-volatile semiconductor storage device includes a gate insulating film formed on a semiconductor substrate, a gate electrode formed on the gate insulating film, and first and second spaced apart doped regions formed below the gate insulating film and the gate electrode in the semiconductor substrate, wherein a grounded region of the first and second spaced apart doped regions is grounded via a contact.