Non-Volatile Memory Device Fabrication with Alternating Charge Layers
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Solution Overview
Problem
Conventional non-volatile memory devices with fin-type structures face integration limitations due to patterning issues during the fin forming process, which restrict their degree of integration and performance.
Innovation Solution
A method of fabricating a non-volatile memory device involving the formation of semiconductor layers with alternating lower and upper charge storing layers and control gate electrodes, along with a string erase electrode, to enhance integration by arranging these elements alternately and removing upper portions to increase packing density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If a fin-type structure is used to improve integration and performance, then higher integration is achieved, but patterning issues limit the degree of integration
Solution Approach 1:
The patent transitions from a planar structure to a three-dimensional structure by forming charge storing layers and control gate electrodes in alternating upper and lower arrangements around the semiconductor layer. This vertical stacking in multiple dimensions enables higher integration density without relying solely on planar patterning, thereby overcoming the patterning limitations of conventional fin-type structures.
Solution Approach 2:
The patent implements a nested structure where lower charge storing layers and lower control gate electrodes are positioned around the bottom surface of the semiconductor layer, while upper charge storing layers and upper control gate electrodes are positioned around the top surface. This nested arrangement of multiple functional layers in three-dimensional space maximizes the use of available volume and achieves higher integration.
2Quantity of substance
If upper portions of charge storing layers and control gate electrodes are removed to increase packing density, then integration degree increases, but device complexity increases
Solution Approach 1:
The patent divides the charge storing layers and control gate electrodes into distinct lower and upper portions, with the upper portions being selectively removed. This segmentation allows independent processing of different regions, enabling the removal of unnecessary upper portions while maintaining the functional lower portions, thereby increasing packing density through selective elimination rather than complex reconfiguration.
Solution Approach 2:
The patent extracts and removes the upper portions of the charge storing layers and control gate electrodes after formation, retaining only the lower portions that are necessary for device function. This extraction process eliminates redundant structures that would occupy space, thereby increasing packing density and integration degree while simplifying the final device structure by removing unnecessary components.
Data Source
AI summary
A method of fabricating a non-volatile memory device according to example embodiments may include forming a semiconductor layer on a substrate. A plurality of lower charge storing layers may be formed on a bottom surface of the semiconductor layer. A plurality of lower control gate electrodes may be formed on the plurality of lower charge storing layers. A plurality of upper charge storing layers may be formed on a top surface of the semiconductor layer. A plurality of upper control gate electrodes may be formed on the plurality of upper charge storing layers, wherein the plurality of lower and upper control gate electrodes may be arranged alternately.